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ZR36015

RASTER TO BLOCK CONVERTER

Unspecified 

PRELIMINARY

ZR36015

FUNCTIONAL DESCRIPTION

The ZR36015 performs conversion between raster and block

formatted data, with applications in image compression and

expansion. It is designed to work with the ZR36050 JPEG

Codec.

Figure 1 is a block diagram of the ZR36015.

The ZR36015 is a programmable device with an asynchronous

Host Interface (WR,RD,ADD(1:0) which is enabled by the SPH

input . Data is transferred between the Host and the ZR36015

internal Control Registers and configuration tables via the

PXDATA(7:0) bus. Because PXDATA(7:0) is used to transfer

data to/from the Host, and also for pixel data, an external buffer

is required to prevent bus contention.

The internal control registers of the ZR36015 consist of four reg-

isters which set the operating mode of the device and control the

interface between the host and the configuration tables. The

configuration tables are used to specify an active window within

the region defined by the VEN and HEN inputs, and to count the

actual number of lins that were processed.

The ZR36015 interfaces to a pixel data bus PXDATA(15:0),

which transfers 4:0:0, 4:1:1, or 4:2:2 formatted data. Transfer of

data on the Pixel Bus is controlled by the Verticle Enable (VEN)

and Horizontal Enable (HEN) inputs.

During Compression, Pixel data can be optionally decimated by

2 in the horizontal direction.

When the ZR36015 is interfaced to the ZR36011 “Color Space

Converter”, then it is recommended that the Clock for Color

Space Converter (CLKCSC) output be connected to the input

clock for the ZR36011.

The ZR36015 supports a double buffered Strip Buffer SRAM

architecture, with up to 64K 16 bit words. The Strip Buffer stores

the image data in interleaved block format. Interleaved block for-

matted data is transferred between the ZR36015 and the

ZR36050 over the BDATA bus.

The ZR36015 can be directly interfaced with the ZR36050 JPEG

Codec. Block transfers of data are controlled by the DSYNC,

STOP, EOS, COE signals, with data being transferred on the

BDATA(7:0) bus. These signals are connected directly to the

ZR36050 DSYNC, STOP, EOS, COMP, and PIXEL(11:4)

signals respectively.

Overflows or underflows of the double buffered Strip Memroy

are indicated by the CBSY output.

The figure shows A/D and D/A conversion devices in between

an image source/display and the ZR36011 (Color Space Con-

verter).

The bus between the ZR36011 and the D/A and A/D converter-

ters is in 24 bit RGB format.

In Compression mode the ZR36011 converts the RGB data into

YUV (luminance/chrominance) data for more efficient compres-

sion.

In Compression mode, the ZR36015 (Raster to Block Convert-

er), converts the raster data into 8x8 blocks for processing by the

ZR36050 JPEG Codec. The SRAM strip buffer stores 8 lines of

data for conversion into block format.

In Compression mode, the ZR36050 JPEG Codec performes

JPEG compression on the block data, and transfers the com-

pressed image over the system bus.

In expansion mode, the process described above is reversed.

The ZR36015 and ZR36050 devices are programmed via the

system bus, and require minimal host intervention during the

compression/expansion processes.

Image Source/Display

24

24

A/D Converter

24

Digital RGB

24

D/A Converter

24

24

ZR36011

Color Space Converter

Digital YUV

ZR36015

16

SRAM Strip Buffer for

Raster to Block Converter

Raster ⇔ Block Conversion

YCbCr

ZR36050

JPEG Image Processor

System Bus

Figure 3. ZR36015 System Configuration Example

Control Registers

The ZR36015 has four Control Registers which allow the Host to

set the mode of operation, and to initiate, terminate, and monitor

System Configuration Example

An example of the ZR36015 system configuration is given in

Figure 3. This figure shows an image compression/expansion

system which uses the ZR36011 (Color Space Converter) and

the ZR36050 (JPEG Codec), in addition to the ZR36015.

3

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