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ZR36015

RASTER TO BLOCK CONVERTER

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PRELIMINARY

ZR36015

CODER BUSY SIGNAL (CBSY)

Before changing over from the A/B face to the A’/B’ face of from the A’/B’ face to the A/B face the CBSY signal must not be active.

The CBSY signal is active under the following conditions.

1. In compression, when all of the pixel data for the active window have been written to the Strip Memory, then CBSY will be asserted

if the Coder has not yet read out all data from the other side of the Strip Memory Buffer.

2. In expansion, when all of the pixel data for the current frame has been read out of one face of the double buffered Strip Memory,

and the Coder has not yot filled the other side of the buffer with data for the next frame.

In either Compression or Expansion, if CBSY is set, then the first HEN signal (for the next strip) should not be asserter until the CBSY

signal becomes inactive.

Factors which can alleviate system problems which are caused by CBSY, are the use of decimation and/or the reduction of the “active

image area”.

CONDITIONS FOR CBSY IN ENCODING MODE

The following sections describe the CBSY signal in relation to the timing for loading and unloading the strip memory. Examples are

given for the encoding and for the decoding modes.

The Strip Memory is double buffered, with one buffer being represented by the A,B memories, and the othre buffer represented by

the A’,B’ memories (see figure TBD). For the purpose of the following discussions, we assume that we start loading to the AB side of

the Strip Buffer, and then load the A’B’ side of the strip buffer (see references to AB,A’B’ in figures TBD-TBD).

Encoding Examples of CBSY Timing

Example #1 : No CBSY

Figure 12 shows an example in encoding mode, where the CBSY is not issues.

Referring to Figure 12, following sequence of events occur...

1. HEN goes HIGH, (indicating the start of the last line of a strip. The ZR36015 begins to count HDelay in order to ingnore the first

HDelay pixels of the line.

2. DSYNC active indicates that data for Strip Buffer AB (previously loaded) is being unloaded to the Coder Bus.

3. The ZR36015 finishes counting HDelay; data for Strip Buffer A’B’ continues to be loaded from the Pixel bus.

4. Readout of data from the A’B’ side of the strip buffer is complete. The ZR36015 checks to make sure that the AB side of the Strip

Buffer is full before switching sides to begin reading data from the AB side to the Code Buffer. In Example 1, The first DSYNC for

the next strip is not issues immediately because the A’B’ side of the Strip Buffer is still being loaded.

5. The writing of a strip to the A’B’ side of the Strip Buffer is complete. At this time the Coder side switches, and data from the A’B’

side of the strip buffer starts to be read out to the Coder interface, as indicated by the active DSYNC signal.

In Example 1, no CBSY was generated because when the strip being loaded into the A’B’ side of the Strip Buffer was completed, the

AB side of the code buffer was already empty and the Pixel Side was able to switch to the AB side immediately in order to begin

writing the next strip.

We assummed in Example 1 that STOP was not active, otherwise new DSYNCs would not be issued (i.e. the ZR36015 would not

write data to the ZR36050 Codec) until the STOP signal became inactive.

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