Introduction
The V320USC Universal System Controller simplifies the design of systems based on MIPS and SuperH microprocessors by replacing many lower integration support components with a single, highintegration device. This saves design time, board area, and manufacturing cost.

Device Highlights
• Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI bus
• Fully compliant with PCI 2.2 specification
• Configurable for primary master, bus master, or target operation
• SDRAM controller with support for Enhanced SDRAM
• Up to 1 KB burst access to (E)SDRAM from PCI, 32 bytes from local processor (MIPS mode)
• 640 bytes of on-chip FIFO storage with Dynamic Bandwidth Allocation™ architecture
• On-the-fly byte order (endian) conversion
• I2O Ready™ ATU and messaging unit
• Programmable chip select / peripheral device strobe generation
• Hot Swap Ready (PICMG™ Hot Swap Specification 2.1)
• Implementation of PCI Bus Power Management Interface Specification Version 1.0
• 3.3 V operation with 5V tolerant inputs
• 208-pin PQFP package
• Up to 75 MHz local bus clock with separate asynchronous PCI clock up to 50 MHz
• Two 32-bit timers
• Initialization through local processor, PCI or serial EEPROM