V320USC-75LPREVB1 Просмотр технического описания (PDF) - QuickLogic Corporation

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V320USC-75LPREVB1

PCI System Controller for 32-Bit MIPS™ and SuperH™ System Interface

QuickLogic Corporation 

V320USC Universal System Controller Rev. G

Signal Description

Table 3 through Table 8 describe the function of each pin on the V320USC.

Signal

AD[31:0]

C/BE[3:0]

PAR

FRAME

IRDY

TRDY

STOP

DEVSEL

IDSEL

PERR

SERR

REQ

GNT

PCLK

Type

PCI I/O

PCI I/O

PCI I/O

PCI I/O

PCI I/O

PCI I/O

PCI I/O

PCI I/O

PCI I

PCI I/O

PCI

I/OD

PCI O

PCI I

PCI I

Table 3: Signal Description—PCI Bus Interface

Ra

Description

Z Address and data, multiplexed on the same pins.

Z Bus Command and Byte Enables, multiplexed on the same pins.

Z Parity represents even parity across AD[31:0] and C/BE[3:0].

Z Cycle Frame indicates the beginning and burst length of an access.

Z

Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the

current data phase of the transaction.

Z

Target Ready indicates the target agent’s (selected device’s) ability to complete the

current data phase of the transaction.

Z

Stop indicates the current target is requesting the master to stop the current transaction

(retry or disconnect).

Device Select, when actively driven by a target, indicates the driving device has

Z decoded its address as the target of the current access. As an input to the initiator,

DEVSEL indicates whether any device on the bus has been selected.

Initialization Device Select is used as a chip select during configuration read and write

transactions. It must be driven high in order to access the chip’s internal configuration

space.

Z

Parity Error is used to report data parity errors during all PCI transactions except a

Special Cycle.

Z

System Error is used to report address parity errors, data parity errors on the Special

Cycle command, or any other system error where the result will be catastrophic.

Z Request indicates to the arbiter that this agent requests use of the bus.

Grant indicates to the agent that access to the bus has been granted.

PCLK provides timing for all transactions on the PCI bus.

a. R indicates state during reset.

Signal

Type

SYSAD[31:0] I/O

SYSCMD[8:0] I/O

VALIDIN

O8

VALIDOUT

I

RELEASE

I

WRRDY

O8

LCLK

I

Table 4: Signal Description—Local Bus Interface, MIPS™ Mode

R

Description

Z System Address / Data (multiplexed)

Z

System Command / data identifier. When MODE0 = ‘0’, SYSCMD[8:5] should be pulled

high.

Z

Valid command or data from external agent. This signal should have an external pull-up

resistor.

Valid command or data from MIPS™

Release the system interface to slave state

Z Write Ready: this signal should have an external pull-up resistor.

Local clock

© 2005 QuickLogic Corporation

www.quicklogic.com

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