V320USC-75LPREVB1 Просмотр технического описания (PDF) - QuickLogic Corporation

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V320USC-75LPREVB1

PCI System Controller for 32-Bit MIPS™ and SuperH™ System Interface

QuickLogic Corporation 

V320USC Universal System Controller Rev. G

Signal

SCL

IOC[11:0]

INT[3:0]

Table 6: Signal Description—DRAM and Peripheral Bus Interface (Continued)

Type

O2

I/O8

PCI

I/OD

R

Description

Z Serial EEPROM Clock

Z Multi-purpose I/O that can be configured for many functions

Z

General purpose interrupt inputs/outputs: may be used for either PCI or local processor

interrupts

Signal

RSTIN

RSTOUT

CH

MODE2:1

MODE0

Type

I

O8

I

I/O8

I

Table 7: Signal Description—Mode and Reset

R

Description

Reset Input: Active low reset input used to initialize all internal functions of the chip.

Reset Output: Driven active when the input reset is driven active. Driven inactive when

0 the RSTOUT bit in the system register is set. The RSTOUT signal is synchronous to

the rising edge of LCLK.

PCI Precharge Bias: This signal is driven low to activate the on-chip precharge bias for

use in PICMG Hot Swap applications. Non-Hot Swap applications should pull this signal

high.

MODE Input: selects the CPU mode:

MODE

2

1

0

Description

Pin 55

Pin 54

Pin 202

Z

SYSCMD7 SYSCMD8

‘H’

‘H’

‘H’

‘L’

MIPS with 9 bit SYSCMD

MIPS with 5 bit SYSCMD

‘H’

‘L’

‘L’

SH3

‘L’

‘L’

‘L’

SH4

others

reserved

‘H’ - Tie High with a weak pull up of 4.7–10K Ω

‘L’ - Tie Low with a weak pull down of 4.7–10K Ω

Signal

VCC

GND

NC

’H’

Type

-

-

-

-

Table 8: Signal Description—Power and Ground Signals

R

Description

POWER leads for external connection to a 3.3V VCC board plane.

GROUND leads for external connection to a GND board plane.

No connect.

Tie High with a weak pull up of 4.7K-10K

© 2005 QuickLogic Corporation

www.quicklogic.com

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