V320USC-75LPREVB1 Просмотр технического описания (PDF) - QuickLogic Corporation
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V320USC-75LPREVB1
QuickLogic Corporation
V320USC-75LPREVB1 Datasheet PDF : 18 Pages
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V320USC Universal System Controller Rev. G
Table 19: PCI Bus Timing Parameters for Vcc = 3.3 Volts +/- 10%
Number
1
2
2a
3
4
4a
5
6
7
Symbol
TC
TSU
TSU
TH
TCOV
TCOV
TCZO
TCOZ
TRST
Description
PCLK period
Synchronous input setup to PCLKa
Synchronous input setup to PCLK (GNT)
Synchronous input hold from PCLK
PCLK to output valid delayb
PCLK to output valid delay (REQ)
PCLK to output driving delay
PCLK to high impedance delay
Reset period
Min.
Max.
Unit
20
ns
7
ns
10
ns
0
ns
2
11
ns
2
12
ns
2
11
ns
3
14
ns
16·TC
a. All PCI signals except GNT.
b. All PCI signals except REQ.
Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms generated
are shown in Figure 3.
Figure 3: Serial EEPROM Waveforms and Timings
START CONDITION
512 PCI BUS
CLOCKS
STOP CONDITION
SCL
SDA
256 PCI BUS
CLOCKS
256 PCI BUS
CLOCKS
10
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