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V320USC-75LPREVB1

PCI System Controller for 32-Bit MIPS™ and SuperH™ System Interface

QuickLogic Corporation 

V320USC Universal System

Controller

• • • • • • PCI System Controller for 32-Bit MIPS™ and SuperH™ System Interface

Device Highlights

• Glueless interface between popular MIPS™ and

SuperH™ processors and the standard 32-bit PCI

bus

• Fully compliant with PCI 2.2 specification

• Configurable for primary master, bus master, or

target operation

• SDRAM controller with support for Enhanced

SDRAM

• Up to 1 KB burst access to (E)SDRAM from PCI,

32 bytes from local processor (MIPS mode)

• 640 bytes of on-chip FIFO storage with Dynamic

Bandwidth Allocation™ architecture

• On-the-fly byte order (endian) conversion

• I2O Ready™ ATU and messaging unit

• Programmable chip select / peripheral device

strobe generation

• Hot Swap Ready (PICMG™ Hot Swap

Specification 2.1)

• Implementation of PCI Bus Power Management

Interface Specification Version 1.0

• 3.3 V operation with 5V tolerant inputs

• 208-pin PQFP package

• Up to 75 MHz local bus clock with separate

asynchronous PCI clock up to 50 MHz

• Two 32-bit timers

• Initialization through local processor, PCI or serial

EEPROM

Introduction

The V320USC Universal System Controller

simplifies the design of systems based on MIPS and

SuperH microprocessors by replacing many lower

integration support components with a single, high-

integration device. This saves design time, board

area, and manufacturing cost.

The I2O Ready V320USC from V3 Semiconductor

is a high performance PCI bridge with integrated

SDRAM controller for MIPS processors operating at

up to 75 MHz bus speed. It features address

translation capabilities and large on-chip buffers. A

separate peripheral bus provides low latency access

to SDRAM. The peripheral controller on the

V320USC also performs address decoding and

chip-select strobes generation for SRAM, PROM

and other slow peripherals.

The integrated SDRAM Controller connects the

processor as well as the PCI bus through on-chip

FIFOs to SDRAM arrays of up to 1 GB in size. The

fully programmable SDRAM controller also supports

the use of Enhanced SDRAM to achieve even

greater performance. Burst accesses of up to 1 KB

from PCI and 32 bytes from the MIPS processor are

supported.

The two general purpose 32-bit timers can be

individually configured as a pulse width modulator, or

used in other modes such as retriggerable or one-

shot. The bus watch timer (MIPS mode) prevents

system hangs during accesses to undecoded regions.

Interrupts for a real time OS can be easily generated

by the system heartbeat timer. A watchdog timer is

also provided for graceful recovery from catastrophic

program failures. Interrupt requests for all on-chip

peripherals are managed by the Interrupt Control

Unit. Additionally, off-chip interrupts can be routed

to the Interrupt Control Unit.

© 2005 QuickLogic Corporation

www.quicklogic.com

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