V320USC-75LPREVB1 Просмотр технического описания (PDF) - QuickLogic Corporation

Номер в каталоге

Компоненты Описание

Список матч

V320USC-75LPREVB1

PCI System Controller for 32-Bit MIPS™ and SuperH™ System Interface

QuickLogic Corporation 

V320USC Universal System Controller Rev. G

Signal

A[31:26]/CS

[5:0]

A[25:0]

D[31:0]

RD/WR

BS

WAIT/RDY

RBE_ENa

Type

I/O8

I

I/O8

I/O8

I/O8

I

O8

I

RBE[3:0]b

I

BREQ

O8

BACK

I

BREQ_INc

I

LCLK

I

Table 5: Signal Description—Local Bus Interface, SH3/4 Mode

R

Description

Z

Upper System Address

Z Lower System Address

Z Data Bus

Z Read/not Write. This is also referred to as MWE for SDRAM

Bus Cycle Start

Z Bus Wait

Enable Read Byte Enables: When active (‘0’), PCI byte lane enables are derived from

RBE[3:0] for a local-to-PCI read access.

Read Byte Enables: provides the byte enable pattern for local-to-PCI read access

when RBE_EN is active. Byte enables for writes are derived from the DQM[3:0]

signals.

Z

Bus Request Output: indicates that the V320USC wants to perform a bus cycle on the

local bus

Bus Acknowledge: asserted to allow the V320USC to take ownership of the local bus.

Bus Request Input: assertion of this input will cause the V320USC to give up

ownership of the local bus at the end of the current burst/single cycle so that a higher

priority master can take ownership. Typically connected to IRQ_OUT.

Local clock. This would be connected to either CKIO on the processor or a clock driver

which provides a clock with the same phase relationship as CKIO. See V3 Reference

Designs for further details.

a. Not available in revision B0 silicon

b. Not available in revision B0 silicon

c. Not available in revision B0 silicon

Signal

MA[14:0]

DCS[3:0]

DQM[3:0]

MBE[3:0]

RAS

CAS

MWE

MAD[31:0]

SDA

Type

O12

O8

I/O8

O12

O12

O12

I/O8

I/OD2

Table 6: Signal Description—DRAM and Peripheral Bus Interface

R

Description

Z

SDRAM Memory Address (also, A[16:2] for peripheral access). MA[14:13] are typically

used for BA[1:0]

Z

SDRAM Chip Select. This should be connected to the CS inputs of SDRAM chips or

DIMM devices.

Z

SDRAM Data Mask for SDRAM access, Byte enables (MBE[3:0]) and A[1:0] for

peripheral access, and write enables for SH3/4 mode access.

Z SDRAM Row Address Strobe

Z SDRAM Column Address Strobe

Z SDRAM Memory Write Enable

Z SDRAM and peripheral bus data. MAD[31:0] is known as D[31:0] when in SH3/4 mode.

Z Serial EEPROM Data

4

•

•••

••

www.quicklogic.com

© 2005 QuickLogic Corporation

Share Link: