PHB101NQ03LT Просмотр технического описания (PDF) - Philips Electronics

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PHB101NQ03LT

TrenchMOS™ logic level FET

Philips Electronics 

Philips Semiconductors

PHB/PHD101NQ03LT

TrenchMOS™ logic level FET

120

Pder

(%)

80

03aa16

120

Ider

(%)

80

03ai19

40

40

0

0

50

100

150

200

Tmb (°C)

Pder = P-------P----t--o--t------- × 100%

t o t ( 25 °C )

Fig 1. Normalized total power dissipation as a

function of mounting base temperature.

103

ID

Limit RDSon = VDS / ID

(A)

102

DC

10

0

0

50

100

150

200

Tmb (°C)

Ider = -I------I---D-------- × 100%

D ( 25 °C )

Fig 2. Normalized continuous drain current as a

function of mounting base temperature.

03ai21

tp = 10 µ s

100 µ s

1 ms

10 ms

1

1

10

VDS (V)

102

Tmb = 25 °C; IDM is single pulse; VGS = 10V.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

9397 750 10929

Product data

Rev. 02 — 25 February 2003

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

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