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AD650KP

Voltage-to-Frequency and Frequency-to-Voltage Converter

Analog Devices 

AD650

Pin 6 at analog ground is opened allowing that voltage to

change. An internal 0.5 mA current source connected to Pin 6

then draws its current out of COS, causing the voltage at Pin 6 to

decrease linearly. At approximately –3.4 V, the one shot resets

itself, thereby ending the timed period and starting the V/F con-

version cycle over again. The total one shot time period can be

written mathematically as:

tOS

=

∆V COS

IDISCHARGE

+ TGATE DELAY

(5)

Figure 2b. Reset Mode

Figure 2c. Integrate Mode substituting actual values quoted above,

tOS

=

–3.4 V × COS

–0.5 × 10–3A

+ 300

× 10–9

sec

(6)

This simplifies into the timed period equation given above.

Figure 2d. Voltage Across CINT

The positive input voltage develops a current (IIN = VIN/RIN)

which charges the integrator capacitor CINT. As charge builds up

on CINT, the output voltage of the integrator ramps downward

towards ground. When the integrator output voltage (Pin 1)

crosses the comparator threshold (–0.6 volt) the comparator

triggers the one shot, whose time period, tOS is determined by

the one shot capacitor COS.

Specifically, the one shot time period is:

tOS = COS × 6.8 × 103 sec /F + 3.0 × 10–7 sec

(1)

The Reset Period is initiated as soon as the integrator output

voltage crosses the comparator threshold, and the integrator

ramps upward by an amount:

( ) dV

∆V = tOS • dt

= tOS

CINT

1mA – IN

(2)

After the Reset Period has ended, the device starts another Inte-

gration Period, as shown in Figure 2, and starts ramping down-

ward again. The amount of time required to reach the

comparator threshold is given as:

TI =

∆V

dV

dt

=

tOS/CINT(1 mA – IIN )

IN /CINT

=

tOS

 1 mA

 IIN

– 1

(3)

The output frequency is now given as:

fOUT

=

1

tOS + TI

=

IIN

tOS × 1 mA

= 0.15

F • Hz

A

VIN /RIN

COS + 4.4 × 10–11F

(4)

Note that CINT, the integration capacitor has no effect on the

transfer relation, but merely determines the amplitude of the

sawtooth signal out of the integrator.

One Shot Timing

A key part of the preceding analysis is the one shot time period

that was given in equation (1). This time period can be broken

down into approximately 300 ns of propagation delay, and a

second time segment dependent linearly on timing capacitor

COS. When the one shot is triggered, a voltage switch that holds

COMPONENT SELECTION

Only four component values must be selected by the user. These

are input resistance RIN, timing capacitor COS, logic resistor R2,

and integration capacitor CINT. The first two determine the

input voltage and full-scale frequency, while the last two are

determined by other circuit considerations.

Of the four components to be selected, R2 is the easiest to de-

fine. As a pull-up resistor, it should be chosen to limit the cur-

rent through the output transistor to 8 mA if a TTL maximum

VOL of 0.4 V is desired. For example, if a 5 V logic supply is

used, R2 should be no smaller than 5 V/8 mA or 625 Ω. A larger

value can be used if desired.

RIN and COS are the only two parameters available to set the full-

scale frequency to accommodate the given signal range. The

“swing” variable that is affected by the choice of RIN and COS is

nonlinearity. The selection guide of Figure 3 shows this quite

graphically. In general, larger values of COS and lower full-scale

input currents (higher values of RIN) provide better linearity. In

Figure 3, the implications of four different choices of RIN are

shown. Although the selection guide is set up for a unipolar con-

figuration with a zero to 10 V input signal range, the results can

be extended to other configurations and input signal ranges. For

a full scale frequency of 100 kHz (corresponding to 10 V input),

you can see that among the available choices, RIN = 20 k and

COS = 620 pF gives the lowest nonlinearity, 0.0038%. Also, if

you wish to use the highest frequency that will give the 20 ppm

minimum nonlinearity, it is approximately 33 kHz (40.2 kΩ and

1000 pF).

For input signal spans other than 10 V, the input resistance

must be scaled proportionately. For example, if 100 kΩ is called

out for a 0 V–10 V span, 10k would be used with a 0 V–1 V

span, or 200 kΩ with a ± 10 V bipolar connection.

The last component to be selected is the integration capacitor

CINT. In almost all cases, the best value for CINT can be calcu-

lated using the equation:

CINT

=

10–4F / sec

f MAX

(1000

pF

minimum)

(7)

When the proper value for CINT is used, the charge balance

architecture of the AD650 provides continuous integration of

the input signal, hence large amounts of noise and interference

–4–

REV. A

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