AD650KP Просмотр технического описания (PDF) - Analog Devices
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AD650KP Datasheet PDF : 12 Pages
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AD650–SPECIFICATIONS (@ + 25؇C, with VS = ؎15 V, unless otherwise noted)
Model
AD650J/AD650A
Min
Typ
Max
AD650K/AD650B
Min
Typ
Max
AD650S
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
Full-Scale Frequency Range
Nonlinearity1 fMAX = 10 kHz
Nonlinearity1 fMAX = 100 kHz
Nonlinearity1 fMAX = 500 kHz
Nonlinearity1 fMAX = 1 MHz
Full-Scale Calibration Error2, 100 kHz
Full-Scale Calibration Error2, 1 MHz
vs. Supply3
vs. Temperaturc
A, B, and S Grades
at 10 kHz
at 100 kHz
J and K Grades
at 10 kHz
at 100 kHz
–0.015
0.002
0.005
0.02
0.1
±5
± 10
1
0.005
0.02
0.05
+0.015
–0.015
0.002
0.005
0.02
0.05
±5
± 10
1
0.005
0.02
0.05
0.1
+0.015
–0.015
0.002
0.005
0.02
0.05
±5
± 10
± 75
± 150
± 75
± 150
± 75
± 150
± 75
± 150
1
0.005
0.02
0.05
0.1
+0.015
MHz
%
%
%
%
%
%
% of FSR/V
± 75
± 150
ppm/°C
ppm/°C
ppm/°C
ppm/°C
BIPOLAR OFFSET CURRENT
Activated by 1.24 kΩ Between Pins 4 and 5
0.45
0.5
0.55
0.45
0.5
0.55
0.45
0.5
0.55
mA
DYNAMIC RESPONSE
Maximum Settling Time for Full Scale
Step Input
Overload Recovery Time
Step Input
1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs
1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs 1 Pulse of New Frequency Plus 1 µs
ANALOLG INPUT AMPLIFIER (V/F Conversion)
Current Input Range (Figure 1)
Voltage Input Range (Figure 5)
Differential Impedance
Common-Mode Impedance
Input Bias Current
Noninverting Input
Inverting Input
Input Offset Voltage
(Trimmable to Zero)
vs. Temperature (TMIN to TMAX)
Safe Input Voltage
COMPARATOR (F/V Conversion)
Logic “0” Level
Logic “1” Level
Pulse Width Range4
Input Impedance
0
–10
2 MΩʈ10 pF
1000 MΩʈ10 pF
40
±8
± 30
± VS
–VS
0
0.1
250
+0.6
0
+0.6
0
+0.6
mA
0
–10
0
–10
0
V
2 MΩʈ10 pF
2 MΩʈ10 pF
1000 MΩʈ10 pF
1000 MΩʈ10 pF
100
40
100
40
100
nA
؎20
±8
؎20
±8
؎20
nA
؎4
؎4
؎4
mV
± 30
± 30
µ V/°C
± VS
± VS
C
–1
–VS
–1
–VS
+VS
0
+VS
0
(0.3 × tOS) 0.1
(0.3 × tOS) 0.1
250
250
+1
V
+VS
V
(0.3 × tOS) µs
kΩ
OPEN COLLECTOR OUTPUT (V/F Conversion)
Output Voltage in Logic “0”
ISINK ≤ 8 mA, TMIN to TMAX
Output Leakage Current in Logic “1”
Voltage Range5
0
0.4
100
+36
0
0.4
100
+36
0
0.4
V
100
nA
+36
V
AMPLIFIER OUTPUT (F/V Conversion)
Voltage Range (1500 Ω min Load Resistance)
0
Source Current (750 Ω max Load Resistance)
10
Capacitive Load (Without Oscillation)
+10
0
10
100
+10
0
10
100
+10
V
mA
100
pF
POWER SUPPLY
Voltage, Rated Performance
Quiescent Current
±9
؎18
±9
؎18
±9
8
8
؎18
V
8
mA
TEMPERATURE RANGE
Rated Performance – N Package
Rated Performance – D Package
Storageated Perfor – N Package
Rated Performance – D Package
PACKAGE OPTIONS6
PLCC (P-20A)
Plastic DIP (N-14)
Ceramic DIP (D-14)
0
+70
0
+70
–25
+85
–25
+85
–55
–25
+85
–25
+85
–65
+150
–65
+150
–65
°C
+125
°C
°C
+150
°C
AD650JP
AD650JN
AD650AD
AD650KP
AD650KN
AD650BD
AD650SD
NOTES
1Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a fraction of full scale.
2Full-scale calibration error adjustable to zero.
3Measured at full-scale output frequency of 100 kHz.
4Refer to F/V conversion section of the text.
5Referred to digital ground.
6D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those test are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested on all production units.
–2–
REV. A
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