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ZR36015

RASTER TO BLOCK CONVERTER

Unspecified 

PRELIMINARY

ZR36015

Strip Buffer Capacity

The address range for the strip buffer is 64K (limited by the

number of address bits for the strip buffer memory). Given that

the strip buffer is 16 bits wide, this gives a maximum memory

capacity of 128K bytes that can be accessed.

The raster to block process stores even blocks for each element

in the A strip buffer memory, and the odd blocks for each

element in the B strip bufer memory (see figure TBD). This

divides the storage capacity required for the total strip evenly

between the A and B sides of the memory.

The table below is used to calculate the required total strip buffer

memory capacity (evenly distributed between the A and B

memories) of the strip buffer.

Capacity = 2 x K x L x HWidth x D

Where...

s “2” is required because the strip buffer is double buffered

s K indicates the number of bytes of data required for each

pixel

s L indicates the number of lines of data required to form a strip

s D is equal to “1” for no decimation delected, and is equal to

“1/2” if decimation is selected.

The maximum number of pixels per line that can be entered for

each mode is given in the table below. This number for the

maximum number of pixels per line is determined by the

maximum addressable strip buffer capacity. When less strip

memory is used (i.e., less than 64K x 16-bits), then the numbers

in the table below must be scaled accordingly.

The limitations for the VHeight values are given in the table

below. These limitations are imposed so that the image size cor-

responds to a complete Minimum Configurable Unit (as defined

in the JPEG specification)

MOD (1:0)

k

1

0

(1:0:0)

1

8

1

4:2:2)

2

8

2

(4:1:1)

1.5

16

3

(4:1:1)

1.5

8

HWidth is limited as shown below:

MOD (1:0)

HWidth maximum value

(Maximum number of pixels in

horizontal direction)

HWidth minimum value

(Minimum number of pixels in

horizontal dirction)

Setting value of HWidth

0

1

2

3

(1:0:0) (4:2:2) (4:1:1) (4:1:1)

8192 4096 2720 5440

8

16

16

32

Multiple Multiple Multiple Multiple

of 8

of 16 of 16 of 32

MOD (1:0)

0

1

2

3

(1:0:0) (4:2:2) (4:1:1) (4:1:1)

HWidth maximum value

(Maximum number of pixels in

horizontal direction)

16384 8192

5440 10880

HWidth minimum value

(Minimum number of pixels in

16

32

32

64

horizontal dirction)

Setting value of HWidth

Multiple Mulitple Multiple Multiple

of 16 of 32 of 32 of 64

The limitations to PAY are such that the maximum value is 8192

lines and the minimum value for each format is as shown below:

MOD (1:0)

0

1

2

3

(1:0:0) 4:2:2) (4:1:1) (4:1:1)

VWIdth minimum value

(Minimum number of lines in vertical

8

direction)

8

16

8

Setting value of VWIdth

Multiple Multiple Multiple Multiple

of 8

of 8 of 16 of 8

Coder Bus Interface

The ZR36015 Raster to Block Converter interfaces directely to

the ZR36050 JPEG Codec.

The Coder Bus Interface consists of the DSYNC, BDATA(7:0),

STOP, EOS, and COE signals (see figure 2).

The Direction of these interface for each mode of operation is

given in the table below.

Table 5: Coder Bus Interface

Signal

Compression Mode

(EDC = 0)

Expansion Mode

(EDC = 1)

DSYNC

Output

Input

BDATA (7:0)

Output

Input

STOP

Input

Output

EOS

Output

Input

COE

Input

Input

The data transfer rate on BDATA(7:0) is equal to the SYSCLK

rate for all formats.

The mode of operation is determined by the “EDC” bit in the

Mode Register when the GO bit is asserted.

Bidirectional signals are availiable as inputs immediately after a

hard reset, and as outputs after the GO bit in the Mode Register

has been set.

The COE signal enables the outputs of the bidirectional signals

of the Code Bus Interface. When COE is High, the outputs for

Compression Mode are enabled, when COE is Low, the output

for Expansion mode are enabled. When the ZR36015 is used

19

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