PSMN102-200Y Просмотр технического описания (PDF) - NXP Semiconductors.

Номер в каталоге

Компоненты Описание

Список матч

PSMN102-200Y

N-channel TrenchMOS standard level FET

NXP Semiconductors. 

NXP Semiconductors

PSMN102-200Y

N-channel TrenchMOS standard level FET

3. Ordering information

Table 2. Ordering information

Type number

Package

Name

PSMN102-200Y

LFPAK

Description

plastic single-ended surface-mounted package; 4 leads

4. Limiting values

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

VDS

drain-source voltage

25 °C ≤ Tj ≤ 150 °C

-

VDGR drain-gate voltage

25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ

-

VGS

gate-source voltage

-

ID

drain current

Tmb = 25 °C; VGS = 10 V; see Figure 2 and 3

-

Tmb = 100 °C; VGS = 10 V; see Figure 2

-

IDM

peak drain current

Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3

-

Ptot

total power dissipation

Tmb = 25 °C; see Figure 1

-

Tstg

storage temperature

−55

Tj

junction temperature

−55

Source-drain diode

IS

source current

Tmb = 25 °C

-

ISM

peak source current

Tmb = 25 °C; pulsed; tp ≤ 10 µs

-

Avalanche ruggedness

EDS(AL)S non-repetitive drain-source

unclamped inductive load; ID = 10.8 A;

-

avalanche energy

tp = 0.14 ms; VDS ≤ 200 V; RGS = 50 Ω;

VGS = 10 V; starting at Tj = 25 °C

Version

SOT669

Max Unit

200

V

200

V

±20

V

21.5 A

13.6 A

65

A

113

W

+150 °C

+150 °C

52

A

208

A

202

mJ

PSMN102-200Y_1

Product data sheet

Rev. 01 — 29 April 2008

© NXP B.V. 2008. All rights reserved.

2 of 12

Share Link: