LH52D1000 Просмотр технического описания (PDF) - Sharp Electronics

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LH52D1000

CMOS 1M (128K × 8) Static Ram

Sharp Electronics 

CMOS 1M (128K × 8) Static RAM

CE1 CONTROL (NOTE)

CE2 CONTROL

VCC

2.7 V

CE1

2.2 V

VCCDR

0V

DATA RETENTION MODE

tCDR

tR

CE1 ≥ VCCDR - 0.2 V

VCC

CE2

2.7 V

VCCDR

0.6 V

DATA RETENTION MODE

tCDR

tR

0V

CE2 ≤ 0.2 V

NOTE: To control the data retention mode at CE1, fix the input level of CE2

between VCCDR and VCCDR - 0.2 V or 0 V to 0.2 V during the data retention mode.

Figure 6. Data Retention

(CE1 Controlled)

LH52D1000

52D1000S-6

9

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