LH52D1000 Просмотр технического описания (PDF) - Sharp Electronics

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LH52D1000

CMOS 1M (128K × 8) Static Ram

Sharp Electronics 

LH52D1000

CMOS 1M (128K × 8) Static RAM

A0 20

A1 19

A2 18

A3 17

A4 16

A5 15

A6 14

A7 13

A8 3

A9 2

A10 31

A11 1

A12 12

A13 4

A14 11

A15 7

A16 10

CE1 30

CE2 6

WE 5

OE 32

10

ROW 1024

DECODER

ADDRESS

BUFFER

7

COLUMN 128

DECODER

MEMORY

CELL ARRAY

(1024 x 128 x 8)

128 x 8

COLUMN GATE

8

CE

CONTROL

LOGIC

OE, WE

CONTROL

LOGIC

I/O BUFFER

21 22 23 25 26 27 28 29

I/O1 I/O2 I/O3 I/O4 I/O5I/O6 I/O7I/O8

Figure 2. LH52D1000 Block Diagram

8 VCC

24 GND

52D1000S-2

PIN DESCRIPTION

SIGNAL

A0 – A16

CE1

CE2

WE

OE

PIN NAME

Address inputs

Chip enable 1

Chip enable 2

Write enable

Output enable

SIGNAL

I/O1 – I/O8

VCC

GND

NC

PIN NAME

Data inputs and outputs

Power supply

Ground

No connection

2

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