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RT5370N

CMOS Technology with PA, LNA, RF, Baseband, and MAC Integrated

Unspecified 

RT5370

Datasheet

3.3 TEST registers

Revision August 30, 2010

RF_CSR_CFG (offset: 0x0500, default: 0x0000_0000)

Bits Type Name

Description

31:18 R

Reserved

17 R/W1 RF_CSR_KICK

Write – kick RF register read/write

0: do nothing 1: kick read/write process

Read – Polling RF register read/write

0: idle

1: busy

16 R/W RF_CSR_WR

0: read 1: write

15:14 R

Reserved

13:8 R/W TESTCSR_RFACC_REGNUM RF register ID R0 ~ R63

0 for R0, 1 for R1 and so on.

7:0 R/W RF_CSR_DATA

Write – DATA written to RF

Read – DATA read from RF

Init Value

0

0

0

0

0

0

RF_SETTING (offset: 0x0504, default: 0x0000_0005)

Bits Type Name

Description

31:23 R

Reserved

22:21 R/W TESTCSR_RF_LNA0

RF_LNA0 value in test mode

20:16 R/W TESTCSR_RF_VGA0

RF_VGA0 value in test mode

15:10 R

Reserved

9 R/W TESTCSR_RF_PA_PE_G0 RF_PA_PE_G0 value in test mode

8 R/W TESTCSR_RF_DC_CAL_EN0 RF_DC_CAL_EN0 value in test mode

7:3 R

Reserved

2 R/W TESTCSR_RF_LDO123_PE LDO123_PE value in test mode

1 R/W TESTCSR_RF_TR

RF_TR value in test mode

0 R/W TESTCSR_RF_PE

RF_PE value in test mode

Init Value

0

0

0

0

0

0

0

1

0

1

RF_TEST_CONTROL (offset: 0x0508, default: 0x0000_0000)

Bits Type Name

Description

31:9 R

Reserved

8 R/W RF_LNA_PE_G0

RF LNA PE G0 value

7:4 R

Reserved

3 R/W RF_TRSW_ANT1

TR switch antenna 1

2 R/W RF_ANT_SEL

RF antenna select

1 R/W TSSI0PSI1

0: ADC6 is used for TSSI

1: ADC6 is used for PSI

0 R/W BYPASS_RF

When set, RF control signals come from RF_SETTING

instead of MAC/BBP in normal operation mode

Init Value

0

0

0

0

0

0

0

PTN_CTRL (offset: 0x0540, default: 0x0008_1000)

Bits Type Name

Description

31 R DATA_DETECT_EN

After detect valid data, It starts to store data into memory.

That is for MEM mode.

30 R/W PTN_REPEAT

Continuously repeat PTN

29 R/W PTN_ADC6_MODE

SWITCH PTN Rx source to ADC6

28 R/W

Reserved

27 R/W PTN_LPBK_SEL_RX0

PTN loop back path via RX0

26:25 R/W PTN_MODE

PTN mode selection:

0: RAMP 1: SINE 2: MEM_I 3:MEM_Q

24 R/W PTN_ACCESS_MEM

Indicate PTN is accessing MEM

Init Value

0

0

0

0

0

0

0

DSRT5370_ V1. 0_083010

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

- 18 -

Ret. Time： 5 Years

Draft

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