RT5370N Просмотр технического описания (PDF) - Unspecified
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RT5370N Datasheet PDF : 70 Pages
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RT5370
Datasheet
2
W1C READ_TX1Q
1
W1C READ_TX2Q
0
W1C READ_RX0Q
Manual read Tx1Q.
Manual read Tx2Q
Manual read Rx0Q
Revision August 30, 2010
0
0
0
MCU_INT_STA (offset:0x0414,default :0x00000000)
Bits Type Name
Description
31:28
Reserved
27
R/W MAC_INT_11
MAC interrupt 11: Reserved
26
R/W MAC_INT_10
MAC interrupt 10: Reserved
25
R/W MAC_INT_9
MAC interrupt 9: Reserved
24
R/W MAC_INT_8
MAC interrupt 8: RX QoS CF-Poll interrupt
23
R/W MAC_INT_7
MAC interrupt 7: TXOP early termination interrupt
22
R/W MAC_INT_6
MAC interrupt 6: TXOP early timeout interrupt
21
R/W MAC_INT_5
MAC interrupt 5: Reserved
20
R/W MAC_INT_4
MAC interrupt 4: GP timer interrupt
19
R/W MAC_INT_3
MAC interrupt 3: Auto wakeup interrupt
18
R/W MAC_INT_2
MAC interrupt 2: TX status interrupt
17
R/W MAC_INT_1
MAC interrupt 1: Pre-TBTT interrupt
16
R/W MAC_INT_0
MAC interrupt 0: TBTT interrupt
15:13
Reserved
12
R/W N2TX_INT
NULL2 frame Tx complete interrupt.
11
R/W DTX0_INT
DMA to TX0Q frame transfer complete interrupt.
10
R/W DTX1_INT
DMA to TX1Q frame transfer complete interrupt.
9
R/W DTX2_INT
DMA to TX2Q frame transfer complete interrupt.
8
R/W DRX0_INT
RX0Q to DMA frame transfer complete interrupt.
7
R/W HCMD_INT
Host command interrupt.
6
R/W N0TX_INT
NULL0 frame Tx complete interrupt.
5
R/W N1TX_INT
NULL1 frame Tx complete interrupt.
4
R/W BCNTX_INT
Beacon frame Tx complete interrupt.
3
R/W MTX0_INT
TX0Q to MAC frame transfer complete interrupt.
2
R/W MTX1_INT
TX1Q to MAC frame transfer complete interrupt.
1
R/W MTX2_INT
TX2Q to MAC frame transfer complete interrupt.
0
R/W MRX0_INT
MAC to RX0Q frame transfer complete interrupt.
*This register is only for 8051
Init Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MCU_INT_ENA (offset:0x0418,default :0x00000000)
Bits Type Name
Description
31:28
Reserved
27 R/W MAC_INT11_EN
MAC interrupt 11 enable
26 R/W MAC_INT10_EN
MAC interrupt 10 enable
25 R/W MAC_INT9_EN
MAC interrupt 9 enable
24 R/W MAC_INT8_EN
MAC interrupt 8 enable
23 R/W MAC_INT7_EN
MAC interrupt 7 enable
22 R/W MAC_INT6_EN
MAC interrupt 6 enable
21 R/W MAC_INT5_EN
MAC interrupt 5 enable
20 R/W MAC_INT4_EN
MAC interrupt 4 enable
19 R/W MAC_INT3_EN
MAC interrupt 3 enable
18 R/W MAC_INT2_EN
MAC interrupt 2 enable
17 R/W MAC_INT1_EN
MAC interrupt 1 enable
16 R/W MAC_INT0_EN
MAC interrupt 0 enable
DSRT5370_ V1. 0_083010
Form No.：QS-073-F02
Rev.：1
Kept by： DCC
Init Value
0
0
0
0
0
0
0
0
0
0
0
0
- 15 -
Ret. Time： 5 Years
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