RT5370N Просмотр технического описания (PDF) - Unspecified

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RT5370N

CMOS Technology with PA, LNA, RF, Baseband, and MAC Integrated

Unspecified 

RT5370

Datasheet

15:13

12 R/W N2TX_INT_EN

11 R/W DTX0_INT_EN

10 R/W DTX1_INT_EN

9 R/W DTX2_INT_EN

8 R/W DRX0_INT_EN

7 R/W HCMD_INT_EN

6 R/W N0TX_INT_EN

5 R/W N1TX_INT_EN

4 R/W BCNTX_INT_EN

3 R/W MTX0_INT_EN

2 R/W MTX1_INT_EN

1 R/W MTX2_INT_EN

0 R/W MRX0_INT_EN

*This register is only for 8051

Revision August 30, 2010

Reserved

NULL2 frame Tx complete interrupt enable.

0

DMA to TX0Q frame transfer complete interrupt enable.

0

DMA to TX1Q frame transfer complete interrupt enable.

0

DMA to TX2Q frame transfer complete interrupt enable.

0

RX0Q to DMA frame transfer complete interrupt enable.

0

Host command interrupt enable.

0

NULL0 frame Tx complete interrupt enable.

0

NULL1 frame Tx complete interrupt enable.

0

Beacon frame Tx complete interrupt enable.

0

TX0Q to MAC frame transfer complete interrupt enable.

0

TX1Q to MAC frame transfer complete interrupt enable.

0

TX2Q to MAC frame transfer complete interrupt enable.

0

MAC to RX0Q frame transfer complete interrupt enable.

0

TX0Q_IO (offset: 0x041C,default :0x00000000)

Bits Type Name

Description

31:16

Reserved

15:0 R/W TX0Q_IO

TX0Q IO port. This register is used in manual mode.

Init Value

0

TX1Q_IO (offset: 0x0420,default :0x00000000)

Bits Type Name

Description

31:16

Reserved

15:0 R/W TX1Q_IO

TX1Q IO port. This register is used in manual mode.

Init Value

0

TX2Q_IO (offset: 0x0424,default :0x00000000)

Bits Type Name

Description

31:16

Reserved

15:0 R/W TX2Q_IO

TX2Q IO port. This register is used in manual mode.

Init Value

0

RX0Q_IO (offset: 0x0428,default :0x00000000)

Bits Type Name

Description

31:16

Reserved

15:0 R/W RX0Q_IO

RX0Q IO port. This register is used in manual mode.

Init Value

0

BCN_OFFSET0 (offset: 0x042C,default :0xECE8E4E0)

Bits Type Name

Description

31:24 R/W BCN3_OFFSET

Beacon #3 address offset in shared memory. Unit is 64 byte.

23:16 R/W BCN2_OFFSET

Beacon #2 address offset in shared memory. Unit is 64 byte.

15:8 R/W BCN1_OFFSET

Beacon #1 address offset in shared memory. Unit is 64 byte.

7:0 R/W BCN0_OFFSET

Beacon #0 address offset in shared memory. Unit is 64 byte.

Init Value

8’hec

8’he8

8’he4

8’he0

BCN_OFFSET1 (offset: 0x0430,default :0xFCF8F4F0)

Bits Type Name

Description

31:24 R/W BCN7_OFFSET

Beacon #7 address offset in shared memory. Unit is 64 byte.

23:16 R/W BCN6_OFFSET

Beacon #6 address offset in shared memory. Unit is 64 byte.

15:8 R/W BCN5_OFFSET

Beacon #5 address offset in shared memory. Unit is 64 byte.

7:0 R/W BCN4_OFFSET

Beacon #4 address offset in shared memory. Unit is 64 byte.

Init Value

8’hfc

8’hf8

8’hf4

8’hf0

TXRXQ_STA (offset: 0x0434,default :0x22020202)

Bits Type Name

Description

31:24 RO RX0Q_STA

RxQ status

23:16 RO TX2Q_STA

Tx2Q status

DSRT5370_ V1. 0_083010

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Draft Init Value

8’h22

8’h02

- 16 -

Ret. Time： 5 Years

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