RT5370N Просмотр технического описания (PDF) - Unspecified
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RT5370N Datasheet PDF : 70 Pages
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RT5370
3.2 PBF registers
Datasheet
Revision August 30, 2010
SYS_CTRL (offset: 0x0400,default :0x00002000)
Bits Type Name
Description
31:20
Reserved
Shared memory access selection.
19
R/W SHR_MSEL
0: address 0x4000 – 0x7FFF mapping to lower 16kB of shared memory
1: address 0x4000 – 0x5FFF mapping to higher 8kB of shared memory
18:17 R/W PBF_MSEL
Packet buffer memory access selection.
00: address 0x8000 – 0xFFFF mapping to 1st 32kB of packet buffer.
01: address 0x8000 – 0xFFFF mapping to 2nd 32kB of packet buffer.
16 R/W HST_PM_SEL Host program ram write selection. This bit is only for PCI/PCIe mode.
15
Reserved
14 R/W CAP_MODE Packet buffer capture mode.
0: packet buffer in normal mode.
1: packet buffer in BBP capture mode.
13 R/W PME_OEN
PCI and PCIE mode: PCI PME OEN
USB mode: 1: force TR_PE=0, RF_PE = 0. 0: normal function.
12 R/W CLKSELECT
MAC/PBF clock source selection.
0: from PLL
1: from 40MHz clock input
11
R/W PBF_CLKEN
PBF clock enable.
10 R/W MAC_CLK_EN MAC clock enable.
9
R/W DMA_CLK_EN DMA clock enable.
8
Reserved
7
R/W MCU_READY MCU ready. 8051 writes ‘1’ to this bit to inform host internal MCU is
ready.
6:5
Reserved
4
R/W ASY_RESET
ASYNC interface reset. Write ‘1’ to put ASYNC into reset state.
3
R/W PBF_RESET
PBF hardware reset. Write ‘1’ to put PBF into reset state.
2
R/W MAC_RESET MAC hardware reset. Write ‘1’ to put MAC into reset state.
1
R/W DMA_RESET DMA hardware reset. Write ‘1’ to put DMA into reset state.
0
W1C MCU_RESET MCU hardware reset. This bit will be auto-cleared after several clock
cycles.
Init Value
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
HOST_CMD (offset: 0x0404,default :0x00000000)
Bits Type Name
Description
31:0 R/W HST_CMD
Host command code. Host write this register will trigger interrupt to
8051.
Init Value
0
PBF_CFG (offset: 0x0408,default :0x07000016)
Bits Type Name
Description
Init Value
31:27
Reserved
26:24 R/W NULL2_SEL
NULL2 frame buffer selection (reuse beacon buffer).
3’h0
0: use beacon #0 buffer (address set by 0x42C[7:0])
1: use beacon #1 buffer (address set by 0x42C[15:8])
2: use beacon #2 buffer (address set by 0x42C[23:16])
3: use beacon #3 buffer (address set by 0x42C[31:24])
DSRT5370_ V1. 0_083010
Form No.：QS-073-F02
4: use beacon #4 buffer (address set by 0x430[7:0])
5: use beacon #5 buffer (address set by 0x430[15:8])
6: use beacon #6 buffer (address set by 0x430[23:16])
Rev.：1
Kept by： DCC
- 13 -
Ret. Time： 5 Years
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