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RT5370N

CMOS Technology with PA, LNA, RF, Baseband, and MAC Integrated

Unspecified 

RT5370

Datasheet

0

W1C RST_DTX_IDX0 Write 1 to reset to TX_DMATX_IDX0 to 0

Revision August 30, 2010

1’b0

DELAY_INT_CFG (offset:0x0210,default :0x00000000)

Bits Type Name

Description

31 RW TXDLY_INT_EN 1: Enable TX delayed interrupt mechanism.

0: Disable TX delayed interrupt mechanism.

30:24 RW TXMAX_PINT

Specified Max # of pended interrupts.

When the # of pended interrupts equal or grater than the value

specified here or interrupt pending time reach the limit (See bellow),

an Final TX_DLY_INT is generated.

Init Value

1’b0

7’b0

23:16 RW TXMAX_PTIME

Set to 0 will disable pending interrupt count check

Specified Max pending time for the internal TX_DONE_INT0-5. When 8’b0

the pending time equal or grater TXMAX_PTIME x 20us or the # of

pended TX_DONE_INT0-5 equal or grater than TXMAX_PINT (see

above), an Final TX_DLY_INT is generated

15 RW RXDLY_INT_EN

14:8 RW RXMAX_PINT

Set to 0 will disable pending interrupt time check

1: Enable RX delayed interrupt mechanism.

1’b0

0: Disable RX delayed interrupt mechanism.

Specified Max # of pended interrupts.

7’b0

When the # of pended interrupts equal or grater than the value

specified here or interrupt pending time reach the limit (See bellow),

an Final RX_DLY_INT is generated.

Set to 0 will disable pending interrupt count check

7:0 RW RXMAX_PTIME Specified Max pending time for the internal RX_DONE_INT. When the 8’b0

pending time equal or grater RXMAX_PTIME x 20us or , the # of

pended RX_DONE_INT equal or grater than RXMAX_PCNT (see

above), an Final RX_DLY_INT is generated

Set to 0 will disable pending interrupt time check

WMM_AIFSN_CFG (offset:0x0214,default :0x00000000)

Bits Type Name

Description

31:16

Reserved

15:12 RW AIFSN3

WMM parameter AIFSN3

11:8 RW AIFSN2

WMM parameter AIFSN2

7:4 RW AIFSN1

WMM parameter AIFSN1

3:0 RW AIFSN0

WMM parameter AIFSN0

Init Value

4’h0

4’h0

4’h0

4’h0

WMM_CWMIN_CFG (offset:0x0218,default :0x00000000)

Bits Type Name

Description

31:16

Reserved

15:12 RW CW_MIN3

WMM parameter Cw_min3

11:8 RW CW_MIN2

WMM parameter Cw_min2

7:4 RW CW_MIN1

WMM parameter Cw_min1

3:0 RW CW_MIN0

WMM parameter Cw_min0

Init Value

4’h0

4’h0

4’h0

4’h0

WMM_CWMAX_CFG (offset:0x021C,default :0x00000000)

Bits Type Name

Description

31:16

Reserved

15:12 RW CW_MAX3

WMM parameter Cw_max3

11:8 RW CW_MAX2

WMM parameter Cw_max2

7:4 RW CW_MAX1

WMM parameter Cw_max1

3:0 RW CW_MAX0

WMM parameter Cw_max0

DSRT5370_ V1. 0_083010

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Init Value

4’h0

4’h0

4’h0

4’h0

-9-

Ret. Time： 5 Years

Draft

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