MT8960 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT8960

Integrated PCM Filter Codec

Zarlink Semiconductor Inc 

MT8960/61/62/63/64/65/66/67

Data Sheet

Since a single clock frequency of 2.048 MHz is required, all digital data is input and output at this rate. DSTo,

therefore, assumes a high impedance state for all but 3.9 µs of the 125 µs frame. Similarly, DSTi input data is valid

for only 3.9 µs.

Digital Control Functions

CSTi is a digital input (levels GNDD to VDD) which is used to control the function of the filter/codec. It operates in

three different modes depending on the logic levels applied to the Control Address input (CA) and chip enable input

(F1i) (see Table 1).

Mode 1

CA=-5V (VEE); CSTi=0V (GNDD)

The filter/codec is in normal operation with nominal transmit and receive gain of 0dB. The SD outputs are in their

active states and the test modes cannot be entered.

CA = -5V (VEE); CSTi = +5V (VDD)

A state of powerdown is forced upon the chip whereby DSTo becomes high impedance, VR is connected to GNDA

and all analog sections have power removed.

Mode 2

CA= -5V (VEE); CSTi receives an eight-bit control word

CSTi accepts a serial data stream synchronously with DSTi (i.e., it accepts an eight-bit serial word in a 3.9 µs

timeslot, updated every 125 µs, and is specified identically to DSTi for timing considerations). This eight-bit control

word is entered into Control Register A and enables programming of the following functions: transmit and receive

gain, powerdown, loopback. Register B is reset to zero and the SD outputs assume their inactive state. Test modes

cannot be entered.

Mode 3

CA=0V (GNDD); CSTi receives an eight-bit control word

As in Mode 2, the control word enters Register A and the aforementioned functions are controlled. In this mode,

however, Register B is not reset, thus not affecting the states of the SD outputs.

CA=+5V (VDD); CSTi receives an 8-bit control word

In this case the control word is transferred into Register B. Register A is unaffected. The input and output of PCM

data is inhibited.

The contents of Register B controls the six uncommitted outputs SD0-SD5 (four outputs, SD0-SD3, on

MT8960/61/64/65 versions of chip) and also provide entry into one of the three test modes of the chip.

Note: For Modes 1 and 2, F1i must be at logic low for one period of 3.9 µs, in each 125 µs cycle, when PCM data

is being input and output, and the control word at CSTi enters Register A. For Mode 3, F1i must be at a logic low for

two periods of 3.9 µs, in each 125 µs cycle. In the first period, CA must be at GNDD or VEE, and in the second

period CA must be high (VDD).

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Zarlink Semiconductor Inc.

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