MT8960 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT8960

Integrated PCM Filter Codec

Zarlink Semiconductor Inc 

MT8960/61/62/63/64/65/66/67

Data Sheet

Logic Control Outputs SD0-5

These outputs are directly controlled by the logic states of bits 0-5 in Register B. A logic low (GNDD) in Register B

causes the SD outputs to assume an inactive state. A logic high (VDD) in Register B causes the SD outputs to

assume an active state (see Table 3). SD0-2 switch between GNDD and VDD and may be used to control

external logic or transistor circuitry, for example, that employed on the line card for performing such functions

as relay drive for application of ringing to line, message waiting indication, etc.

SD3-5 are used primarily to drive external analog circuitry. Examples may include the switching in or out of gain

sections or filter sections (e.g., ring trip filter) (Figure 7).

MT8962/63/66/67 provides all six SD outputs.

MT8960/61/64/65 each packaged in an 18-pin DIP provide only four control outputs, SD0-3.

2 Wire

Analog

Supervision

Protection

Battery

Feed

Ringing

Telephone Set

2W/4W

Converter

PCM Highway

MT8960/61

MT8962/63

MT8964/65

MT8966/67

Figure 6 - Typical Line Termination

BITS 0-2

0

1

BIT 3

0

1

LOGIC CONTROL OUTPUTS SD0-SD2

Inactive state - logic low (GNDD).

Active state - logic high (VDD).

LOGIC CONTROL OUTPUT SD3

Inactive state - High Impedance.

Active state - GNDA.

BITS 4,5

0

1

LOGIC CONTROL OUTPUTS SD4, SD5

Inactive state - High Impedance.

Active state - GNDD.

BIT 7 BIT 6

CHIP TESTING CONTROLS

0

0 Normal operation.

10

Zarlink Semiconductor Inc.

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