AT76C101 Просмотр технического описания (PDF) - Atmel Corporation

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AT76C101

JPEG Image Compression Processor

Atmel Corporation 

AT76C101

Table 1. Signal Description

Signal

Type

BST_TEST

Input

CLK

Input

FREEZE

Input

MAST_CS

PX_CLK

RESET_

TEST

Input

Input

Input

Input

HSync

M_ADD[19:0]

Bidirectional

Bidirectional

M_DATA[7:0]

Bidirectional

MAST_OE

Bidirectional

MAST_WR

Bidirectional

SRData[15:0]

Bidirectional

VSync

BUSY

Bidirectional

Output

FRAMEND

Output

MEM_CS

Output

PXIN

Output

PXOUT

Output

PXRE

PXWE

SRADD[14:0]

Output

Output

Output

SRDRIVE

stop_pixel

Output

Output

Description

BIST test pin (used only for testing), should be grounded.

Master Clock.

Stall Signal, active high. When this signal is asserted, the chip finishes processing the current

block and then remains in that state until freeze is pulled low.

Master Chip Select Input. Used by microcontroller to access the JPEG chip. Active low.

Video Interface Clock (27 MHz fixed).

Global Reset Signal, active high, minimum pulse width is three CLK_IN 40 MHz cycles.

Active high - Puts chip in test mode. User has access to all internal memory. Must be tied to gnd

for normal operation.

Indicates start of a horizontal line of the frame.

Memory/Microcontroller Address Bus. Used by JPEG chip to access the compressed data

memory, and used by microcontroller to access the JPEG chip.

Memory/ Microcontroller Data Bus. Used to transfer compressed data to the external storage unit.

Also used by microcontroller to program the JPEG chip.

Memory/ Microcontroller Read Select. Active low. Used by microcontroller to read from JPEG

chip and used by JPEG chip to read compressed data from memory.

Memory/Microcontroller Write Select. Active low. Used by microcontroller to write to JPEG and

used by JPEG to write to compressed data memory.

Pixel Data Bus for inputting uncompressed data in encoding mode, or for outputting

decompressed image data in decoding mode.

Indicates the start of a frame.

Microcontroller bus busy.

Signals whether the JPEG chip (high) or microcontroller (low) controls the bus.

End of encoding/decoding operation. FRAMEND is active after chip is reset and it remains active

until the Start Register is set by the host.

Compressed data memory select. Active low. Used by JPEG to select the external memory

device used to store the compressed data stream.

Pixel Input Control. It is asserted low when pixels are being input from the active portion of the

frame into the strip buffer.

Pixel Output Control. It ia active only when the pixels from the active region of the field are being

read from the strip buffer.

Active low. Controls reading data from external memory.

Active low. Controls writing to the external memory.

Pixel Address Bus. This bus specifies the address location of the external memory device (strip

buffer), from/ to which the pixel data is transferred. Supports external memory of up to 32K

locations.

Indicates that the AT76C101 is driving the SRDATA Bus.

When asserted, all operations in the video interface are stopped. Active when the DCT buffers

are full, or when the ext. video logic is not ready.

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