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W83194BR-640

166MHZ CLOCK FOR SIS CHIPSET

Winbond 

W83194BR-640

1. GENERAL DESCRIPTION

The W83194BR-640 is a Clock Synthesizer for SiS 640 chipset. W83194BR-640 provides all clocks

required for high-speed RISC or CISC microprocessor such as Intel Pentium II, Pentium III and

Celeron, and also provides 16 different frequencies of CPU clocks frequency setting. All clocks are

externally selectable with smooth transitions. The W83194BR-640 makes SDRAM in synchronous or

asynchronous frequency with CPU clocks.

The W83194BR-640 provides step-less frequency programming by controlling the VCO freq. and the

programmable AGP, PCI clock output divisor ratio. A watch dog timer is quipped and when time out,

the RESET# pin will output 4ms pulse signal. Spread spectrum built in at ±0.5% or ±0.25% to reduce

EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface

The W83194BR-640 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.

High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU

CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5%

duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns

slew rate.

2. PRODUCT FEATURES

• Supports Intel Slot 1 and Socket 370 CPUs with I2C.

• 2 CPU clocks

• 2 AGP clocks

• 1 SDRAM output clock for chipset

• 1 IOAPIC clock

• 6 PCI synchronous clocks.

• Optional single or mixed supply:

(Others Vdd = 3.3V, VddLCPU=2.5V)

• Skew --- CPU to CPU < 175ps, CPU to SDRAM < 250ps, PCI to PCI < 500ps, AGP to AGP < 175ps

• Smooth frequency switch with selections from 66 to 200mhz

• I2C 2-Wire serial interface and I2C read back

• 0.5%, 0.25%center type, 0~0.5% down type spread spectrum to reduce EMI

• Programmable registers to enable/stop each output and select modes

(mode as Tri-state or Normal )

• 48 MHz for USB

• 24 MHz for super I/O

• Packaged in 48-pin SSOP

Publication Release Date: April. 2001

-2-

Revision 1.0

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