LH28F320BJE-PTTL90 Просмотр технического описания (PDF) - Sharp Electronics

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LH28F320BJE-PTTL90

Flash Memory 32M (2M × 16/4M × 8)

Sharp Electronics 

SHARP

LHF32JO2

4.10 Set Block and Permanent Lock-Bit

Commands

A flexible block locking and unlocking scheme is enabled

via a combination of block lock-bits. a permanent lock-bit

and WP# pin. The block lock-bits and WP# pin gates

program and erase operations while the permanent lock-bit

gates block-lock bit modification. With the permanent

lock-bit not set, individual block lock-bits can be set using

the Set Block Lock-Bit command. The Set Permanent

Lock-Bit command, sets the permanent lock-bit. After the

permanent lock-bit is set, block lock-bits and locked block

contents cannot altered. See Table 5 for a summary of

hardware and software write protection options.

Set block lock-bit and permanent lock-bit are executed by

a two-cycle command sequence. The set block or

permanent lock-bit setup along with appropriate block or

device address is written followed by either the set block

Lock-bit confirm (and an address within the block to be

.ocked) or the set permanent lock-bit confirm (and any

levice address). The WSM then controls the set lock-bit

rlgorithm. After the sequence is written. the device

mtomatically outputs status register data when read (see

?gure 11). The CPU can detect the completion of the set

ock-bit event by analyzing the RY/BY# pin output or

;tatus register bit SR.7.

When the set lock-bit operation is complete. status register

Iit SR.3 should be checked. If an error is detected, the

‘tatus register should be cleared. The GUI will remain in

ead status register mode until a new command is issued.

this two-step sequence of set-up followed by execution

fnsures that lock-bits are not accidentally set. An invalid

;et Block or Permanent Lock-Bit command will result in

tatus register bits SR.4 and SR.5 being set to “1”. Also,

eliable operations occur only when Vcc=2.7V-3.6V and

ICCW=vCCWH1/2~ In the absence of this high voltage,

lck-bit contents are protected against alteration.

L successful set block lock-bit operation requires that the

ermanent lock-bit be cleared. If it is attempted with the

ermanent lock-bit set, SR.1 and SR.4 will be set to “1”

nd the operation will fail.

4.11 Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the Clear

Block Lock-Bits command. With the permanent lock-bit

not set, block lock-bits can be cleared using only the Clear

Block Lock-Bits command. If the permanent lock-bit is

set, block lock-bits cannot cleared. See Table 5 for a

summary of hardware and software write protection

options.

Clear block lock-bits operation is executed by a two-cycle

command sequence. A clear block lock-bits setup is first

written. After the command is written. the device

automatically outputs status register data when read (see

Figure 12). The CPU can detect completion of the clear

block lock-bits event by analyzing the RY/BY# Pin output

or status register bit SR.7.

When the operation is complete, status register bit SR.5

should be checked. If a clear block lock-bit error is

detected, the status register should be cleared. The CUI

will remain in read status register mode until another

command is issued.

This two-step sequence of set-up followed by execution

ensures that block lock-bits are not accidentally cleared.

An invalid Clear Block Lock-Bits command sequence will

result in status register bits SR.4 and SR.5 being set to “1”.

Also, a reliable clear block lock-bits operation can only

occur when V,-=2.7V-3.6V and VCCw=VCCwH1,2. If a

clear block iock-bits operation is attempted while

Vc+V,,,,,

SR.3 and SR.5 will be set to “1”. In the

absence of this high voltage. the block lock-bits content

are protected against alteration. A successful clear block

lock-bits operation requires that the permanent lock-bit is

not set. If it is attempted with the permanent lock-bit set,

SR.1 and SR.5 will be set to “1” and the operation will

fail.

If a clear block lock-bits operation is aborted due to Vccw

or Vcc transitioning out of valid range or RP# active

transition, block lock-bit values are left in an

undetermined state. A repeat of clear block lock-bits is

required to initialize block lock-bit contents to known

values. Once the permanent lock-bit is set. it cannot be

cleared.

Rev. 1.25

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