LH28F320BJE-PTTL90 Просмотр технического описания (PDF) - Sharp Electronics

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LH28F320BJE-PTTL90

Flash Memory 32M (2M × 16/4M × 8)

Sharp Electronics 

SHARP

LHF32JO2

4.5 Block Erase Command

Erase is executed one block at a time and initiated by a

two-cycle command. A block erase setup is first written,

followed by an block erase confirm. This command

sequence requires appropriate sequencing and an address

within the block to be erased (erase changes all block data

to FFFFH/FFH). Block preconditioning. erase. and verify

are handled internally by the WSM (invisible to the

system). After the two-cycle block erase sequence is

written, the device automatically outputs status register

data when read (see Figure 6). The CPU can detect block

erase completion by analyzin_g the output data of the

RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register bit SR.5

should be checked. If a block erase error is detected, the

status register should be cleared before system software

attempts corrective actions. The CUI remains in read

status register mode until a new command is issued.

This two-step command sequence of set-up followed by

execution ensures that block contents are not accidentally

erased. An invalid Block Erase command sequence will

result in both status register bits SR.4 and SR.5 being set

to “1”. Also. reliable block erasure can only occur when

Vcc=2.7V-3.6V and VCCW=VCCwH1,?. In the absence of

this high voltage, block contents are protected against

erasure. If block erase is attempted while VCCWIVCCWLK.

SR.3 and SR.5 will be set to “1”. Successful block erase

requires for boot blocks that WP# is V,, and the

corresponding block lock-bit be cleared. In parameter and

main blocks case, it must be cleard the corresponding

block lock-bit. If block erase is attempted when the

excepting above conditions. SR.1 and SR.5 will be set to

“1”.

4.6 Full Chip Erase Command

I’his command followed by a confirm command erases all

af the unlocked blocks. A full chip erase setup (30H) is

!irst written. followed by a full chip erase confirm (DOH).

4fter a confirm command is written. device erases the all

mlocked blocks block by block. This command sequence

.equires appropriate sequencing. Block preconditioning.

:rase and verify are handled internally by the WSIM

invisible to the system). After the two-cycle full chip

:rase sequence is written. the device automatically outputs

status register data when read (see Figure 7). The CPU can

ietect full chip erase completion by analyzing the output

lata of the RY/BY# pin or status register bit SR.7.

Nhen the full chip erase is complete. status register bit

lR.5 should be checked. If erase error is detected. the

tatus register should be cleared before system software

ittempts corrective actions. The CUI remains in read

status register mode until a new command is issued. I

error is detected on a block during full chip erase

operation. WSIM stops erasing. Full chip erase operatior

start from lower address block. finish the higher addres!

block. Full chip erase can not be suspended.

This two-step command sequence of set-up followed b)

execution ensures that block contents are not accidentall)

erased. An invalid Full Chip Erase command sequence

will result in both status register bits SR.4 and SR.5 being

set to “1”. Also, reliable full chip erasure can only OCCUI

when V,,- -2 7V-3.6V and VCCw=VCCWHln. In the

absence of this high voltage. block contents are protectec

against erasure. If full chip erase is attempted while

V CCWIVCCwrK. SR.3 and SR.5 will be set to “1”

Successful full chip erase requires for boot blocks thal

WP# is V,, and the corresponding block lock-bit be

cleared. In parameter and main blocks case, it must be

cleard the corresponding block lock-bit. If all blocks are

locked. SR.1 and SR.5 will be set to “1”.

4.7 Word/Byte Write Command

Word/Byte write is executed by a two-cycle command

sequence. Word/Byte write setup (standard 40H 01

alternate 10H) is written. followed by a second write that

specifies the address and data (latched on the rising edge

of WE#). The WSM then takes over, controlling the

word/byte write and write verify algorithms internally.

After the word/byte write sequence is written, the device

automatically outputs status resister data when read (see

Figure 8). The CPU can detect the completion of the

word/byte write event by analyzing the RY/BY# pin OI

status register bit SR.7.

When word/byte write is complete, status register bit SR.J

should be checked. If word/byte write error is detected. the

status register should be cleared. The internal WSM verify

only detects errors for “1”s that do not successfully write

to “0”s. The CUI remains in read status register mode until

it receives another command.

Reliable word/byte writes can only occur when

V,,=2.7V-3.6V and VCCw=VCCWHIR. In the absence of

this high voltage. memory contents are protected against

word/byte writes. If word/byte write is attempted while

VCCW<VCCwtK. status register bits SR.3 and SR.4 will be

set to “I”. Successful word/byte write requires for boot

blocks that WP# is V,, and the corresponding block lock-

bit be cleared. In parameter and main blocks case, it must

be cleard the corresponding block lock-bit. If word/byte

write is attempted when the excepting above conditions.

SR. 1 and SR.-l will be set to “I”.

Rev. 1.25

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