LH28F320BJE-PTTL90 Просмотр технического описания (PDF) - Sharp Electronics

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LH28F320BJE-PTTL90

Flash Memory 32M (2M × 16/4M × 8)

Sharp Electronics 

SHARP

LHF32JO2

4.1 Read Array Command

Upon initial device power-up and after exit from reset

mode. the device defaults to read array mode. This

operation is also initiated by writing the Read Array

command. The device remains enabled for reads until

another command is written. Once the internal WSM has

started a block erase, full chip erase. word/byte write or

lock-bit configuration the device will not recognize the

Read Array command until the WSM completes its

operation unless the WSM is suspended via an Erase

Suspend or Word/Byte Write Suspend command. The

Read Array command functions independently of the

Vccw voltage and RP# can be V,,.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing the

Read Identifier Codes command. Following the command

write, read cycles from addresses shown in Figure 4

retrieve the manufacturer, device. block lock configuration

and permanent lock configuration codes (see Table 4 for

Identifier code values). To terminate the operation. write

another valid command. Like the Read Array command,

he Read Identifier Codes command functions

ndependently of the V,-w voltage and RP# can be V,,.

‘allowing the Read Identifier Codes command, the

‘allowing information can be read:

Table 4. Identifier Codes

Code

Address(‘) Data(3)

[A,,-A,1 PQ,-DQ,l

Manufacture Code

OOOOOH BOH

Device Code

Block Lock Configuration

OOOOlH E2H

B A( I,+2 ‘.~,.~..~~~~~ .,.

*Block is Unlocked

DQ,=O

*Block is Locked

DQ,= 1

*Reserved for Future Use

Permanent Lock Configuration

4.3 Read Status Register Command

The status register may be read to determine when a block

erase, full chip erase, word/byte write or lock-bit

configuration is complete and whether the operation

completed successfully. It may be read at any time by

writing the Read Status Register command. After writing

this command, all subsequent read operations output data

from the status register until another valid command is

written. The status register contents are latched on the

falling edge of OE# or CE#, whichever occurs. OE# or

CE# must toggle to VIH before further reads to update the

status register latch. The Read Status Register command

functions independently of the Vccw voltage. RP# can be

VII-t.

4.4 Clear Status Register Command

Status register bits SR.5. SR.4. SR.3 or SR.l are set to

“1”s by the WSM and can only be reset by the Clear Status

Register command. These bits indicate various failure

conditions (see Table 6). By allowing system software to

reset these bits. several operations (such as cumulatively

erasing multiple blocks or writing several words/bytes in

sequence) may be performed. The status register may be

polled to determine if an error occurred during the

sequence.

To clear the status register. the Clear Status Register

command (50H) is written. It functions independently of

the applied Vccw Voltage. RP# can be V,,. This

command is not functional during block erase or

word/byte write suspend modes.

BA selects the specific block lock configuration code

to be read. See Figure 4 for the device identifier code

memory map.

!. A-, don’t care in byte mode.

1. DQtj-DQ9 outputs OOH in word mode.

_I

Rev. 1.25

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