LH28F320BJE-PTTL90 Просмотр технического описания (PDF) - Sharp Electronics

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LH28F320BJE-PTTL90

Flash Memory 32M (2M × 16/4M × 8)

Sharp Electronics 

SHARI=

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LHF32JO2

9

3 BUS OPERATION

The local CPU reads and writes flash memory in-system.

All bus cycles to or from the flash memory conform to

standard microprocessor bus cycles.

3.; Read

Information can be read from any block, identifier codes

or status register independent of the Vccw voltage. RP#

can be at V,.

The first task is to write the appropriate read mode

command (Read Array. Read Identifier Codes or Read

Status Register) to the CUI. Upon initial device power-up

or after exit from reset mode. the device automatically

resets to read array mode. Six control pins dictate the data

flow in and out of the component: CE#, OE#, BYTE#,

WE#, RP# and WP#. CE# and OE# must be driven active

to obtain data at the outputs. CE# is the device selection

control. and when active enables the selected memory

device. OE# is the data output (DQo-DQ,,) control and

when active drives the selected memory data onto the I/O

bus. BYTE# is the device I/O interface mde control. WE#

must be at V,,, RP# must be at V,,. and BYTE# and WP#

must be at V, or V,,. Figure 16. 17 illustrates read cycle.

3.2 Output Disable

With OE# at a logic-high level (V,,). the device outputs

Ire disabled. Output pins (DQ,-DQ,j) are placed in a

ligh-impedance state.

3.3 Standby

C1E# at a logic-high level (V,,) places the device in

standby mode which substantially reduces device power

:onsumption. DQ,-DQ,, outputs are placed in a high-

mpedance state independent of OE#. If deselected during

)lock erase. full chip erase. word/byte write or lock-bit

:onfiguration, the device continues functioning, and

:onsuming active power until the operation completes.

3.4 Reset

RP# at V,, initiates the reset mode.

In read modes: RP#-low deselects the memory. places

output drivers in a high-impedance state and turns off all

internal circuits. RP# must be held low for a minimum of

1OOns. Time tpHQv is required after return from reset

mode until initial memory access outputs are valid. After

this wake-up interval, normal operation is restored. The

CUI is reset to read array mode and status register is set to

80H.

During block erase. full chip erase. word/byte write or

lock-bit configuration modes. RP#-low will abort the

operation. RY/BY# remains low until the reset operation

is complete. Memory contents being altered are no longer

valid; the data may be partially erased or written. Time

tpBwL is required after RP# goes to logic-high (V,,)

before another command can be written.

As with any automated device. it is important to assert

RP# during system reset. When the system comes out of

reset, it expects to read from the flash memory. Automated

flash memories provide status information when accessed

during block erase. full chip erase, word/byte write or

lock-bit configuration modes. If a CPU reset occurs with

no flash memory reset. proper CPU initialization may not

occur because the flash memory may be providing status

information instead of assay data. SHARP’s flash

memories allow proper CPU initialization following a

system reset through the use of the RP# input. In this

application, RP# is controlled by the same RESET# signal

that resets the system CPU.

Rev. 1.15

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