CDB42406 Просмотр технического описания (PDF) - Cirrus Logic

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CDB42406

Evaluation Board For CS42406

Cirrus Logic 

CDB42406

1.7.1 S/PDIF IN & S/PDIF OUT (Setup 0 - Setup 2)

There are 3 different setup options for routing MCLK, LRCK and SCLK for S/PDIF input

and output conversion. These options allow the user to choose between 3 different mas-

ters for the ADC subclocks. Should the CS8416 lose lock to the S/PDIF input, the RMCK

will automatically switch from the PLL to the OMCK input (see the CS8416 datasheet for

details). The CS8406 is always clocked from the same source as the ADC.

1.7.1a Setup 0

Using the recovered clock from the S/PDIF input data stream, the CS8416 masters all

clocks for the ADC and all clocks and data for the DAC. For implementation of this setup

option, set DIP switch S4 (SW[3:0]) to ‘0000’b.

A U D IO

MCLK

CS8416

RM CK

OM CK

O LR CK /

O SCLK

SDOUT

CS8406

OM CK

IL RC K /

IS C LK

SDIN

CS42406

MCLK

DAC_L RCK/

D AC _S C LK

D AC _S D IN x

A D C_ LR CK /

ADC_ SCLK

A DC _S D OU T

DSP I/O

HDR

DSP_MCLK

D S P _D A C_ LRC K /

DSP_DAC_ SCLK

DS P _S D IN x

D S P _A D C_ LRC K /

DSP_ADC_ SCLK

DS P _S D OU T

Figure 1. S/PDIF IN/OUT - Setup 0

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