CDB42406 Просмотр технического описания (PDF) - Cirrus Logic

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CDB42406

Evaluation Board For CS42406

Cirrus Logic 

CDB42406

Evaluation Board For CS42406

Features

Single-ended analog inputs and outputs

CS8406 S/PDIF digital audio transmitter

CS8416 S/PDIF digital audio receiver

Header for optional external configuration of

CS42406

Header for external DSP serial audio I/O

3.3 V to 5.0 V Logic Interface

14 Pre-defined Board Setup Options

Demonstrates recommended layout and

grounding arrangements

Windows compatible software interface to

configure CS42406 and intra-board

connections

ORDERING INFORMATION

CDB42406

I

Evaluation Board

Description

The CDB42406 demonstration board is an excellent

means for evaluating the CS42406 CODEC. Evaluation

requires an analog/digital signal source and analyzer,

and power supplies. Optionally, a Windows PC compat-

ible computer may be used to evaluate the CS42406

DAC in control port mode.

System timing can be provided by the CS42406, by the

CS8416 phase-locked to its S/PDIF input, by an I/O

stake header or by an on-board oscillator. RCA phono

jacks are provided for the CS42406 analog outputs and

inputs. Digital data I/O is available via RCA phono or op-

tical connectors to the CS8416 and CS8406. 14 pre-

defined board setup options are selectable using a 4-po-

sition DIP switch.

The Windows software provides a GUI to make configu-

ration of the DAC easy. The software communicates

through the PC’s parallel port to configure the control

port registers so that all features of the CS42406 can be

evaluated. The evaluation board may also be configured

to accept external timing and data signals for operation

in a user application during system development.

S/PDIF

Output

CS8406 S/PDIF

T ran sm itte r

DAC Control Port

Board

S etup

DA C /A D C

Setup

CP LD

C lo c k /D at a

Router

I2C/SPI

PCM Clock/

D a ta

CS42406

2-Ch.

Single-Ended

Analog Inputs

S /P D IF

Input

CS8416 S/PDIF

Receiver

C ry s ta l

O s c illat o r

Cirrus Logic, Inc.

www.cirrus.com

DSP I/O Header

Master Clock*

6-Ch.

S in g le - E n de d

Analog Outputs

*M aster Clock is selectable between one of the following:

1) S/PDIF R eceiver,

2) C rystal oscillator, or

3) D SP I/O Header.

All selections are buffered.

 Copyright Cirrus Logic, Inc. 2003

(All Rights Reserved)

AUG ‘03

DS614DB1

1

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