CDB42406 Просмотр технического описания (PDF) - Cirrus Logic

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CDB42406

Evaluation Board For CS42406

Cirrus Logic 

CDB42406

1.9 PC Parallel Port Control .................................................................................................. 15

1.10 External Control Headers .............................................................................................. 15

1.11 Power ............................................................................................................................ 16

1.12 Grounding and Power Supply Decoupling ..................................................................... 16

2. BLOCK DIAGRAM ................................................................................................................. 19

3. SCHEMATICS ....................................................................................................................... 20

4. LAYOUT ................................................................................................................................. 30

LIST OF FIGURES

Figure 1. S/PDIF IN/OUT - Setup 0................................................................................................. 6

Figure 2. S/PDIF IN/OUT - Setup 1................................................................................................. 7

Figure 3. S/PDIF IN/OUT - Setup 2................................................................................................. 7

Figure 4. Digital Loopback - Setup 3............................................................................................... 8

Figure 5. Digital Loopback - Setup 4............................................................................................... 9

Figure 6. Digital Loopback - Setup 5............................................................................................... 9

Figure 7. Digital Loopback - Setup 6............................................................................................. 10

Figure 8. DSP Routing - Setup 7................................................................................................... 11

Figure 9. DSP Routing - Setup 8................................................................................................... 11

Figure 10. DSP Routing - Setup 9................................................................................................. 12

Figure 11. DSP Routing - Setup 10............................................................................................... 12

Figure 12. DSP Routing - Setup 11............................................................................................... 13

Figure 13. DSP Routing - Setup 12............................................................................................... 14

Figure 14. No Routing ................................................................................................................... 14

Figure 15. Block Diagram.............................................................................................................. 19

Figure 16. CS42406 ...................................................................................................................... 20

Figure 17. S/PDIF Input ................................................................................................................ 21

Figure 18. S/PDIF Output.............................................................................................................. 22

Figure 19. CPLD ........................................................................................................................... 23

Figure 20. Analog Input................................................................................................................. 24

Figure 21. Ch. 1 Analog Output .................................................................................................... 25

Figure 22. Ch. 2 Analog Output .................................................................................................... 26

Figure 23. Ch. 3 Analog Output .................................................................................................... 27

Figure 24. DAC Control Port and I/O Headers.............................................................................. 28

Figure 25. Power........................................................................................................................... 29

Figure 26. Silk Screen................................................................................................................... 30

Figure 27. Topside Layer .............................................................................................................. 31

Figure 28. Bottomside Layer ......................................................................................................... 32

LIST OF TABLES

Table 1. System Connections ....................................................................................................... 17

Table 2. Jumper/Switch Settings................................................................................................... 18

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