Functional Description
The CY7C1335 is 3.3V 32K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

FEATUREs
• Low (660 µW) standby power (f=0, L version)
• Supports 100-MHz bus for Pentium™ and PowerPC™ operations with zero wait states
• Fully registered inputs and outputs for pipelined operation
• 32K x 32 common I/O architecture
• Single 3.3V power supply
• Fast Clock-to-output times
    — 5.5ns (for 100-MHz device)
    — 7.0 ns (for 75-MHz device)
    — 8.5 ns (for 66-MHz device)
    — 10 ns (for 60-MHz device)
• User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option