CY7C1335 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1335 Datasheet PDF : 15 Pages
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PRELIMINARY
CY7C1335
Switching Characteristics Over the Operating Range[11,12,13]
-100
-75
-66
-60
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC
tCH
tCL
tAS
tAH
tCO
tDOH
tADS
tADH
tWES
Clock Cycle Time
10
13.3
15
16.7
ns
Clock HIGH
3.2
5.0
6.0
6.0
ns
Clock LOW
3.2
5.0
6.0
6.0
ns
Address Set-Up Before CLK Rise
2.0
2.5
2.5
2.5
ns
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
Data Output Valid After CLK Rise
5.5
7.0
8.5
10.0 ns
Data Output Hold After CLK Rise
1.5
2.0
2.0
2.0
ns
ADSP, ADSC Set-Up Before CLK Rise 2.0
2.5
2.5
2.5
ns
ADSP, ADSC Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
BWE, GW, BW[3:0] Set-Up Before CLK 2.0
2.5
2.5
2.5
ns
Rise
tWEH
BWE, GW, BW[3:0] Hold After CLK
0.5
0.5
0.5
0.5
ns
Rise
tADVS
ADV Set-Up Before CLK Rise
2.0
2.5
2.5
2.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tDS
Data Input Set-Up Before CLK Rise
2.0
2.5
2.5
2.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tCES
Chip Select Set-Up
2.0
2.5
2.5
2.5
ns
tCEH
tCHZ
tCLZ
tEOHZ
tEOLZ
tEOV
Chip Select Hold After CLK Rise
Clock to High-Z[12]
Clock to Low-Z[12]
OE HIGH to Output High-Z[12, 13]
OE LOW to Output Low-Z[12,13]
OE LOW to Output Valid[12]
0.5
0.5
0.5
0.5
ns
1.5
5
2
6
2
6
2
6 ns
0
0
0
0
ns
5.5
6
6
6 ns
0
0
0
0
6 ns
5.5
6
6
6 ns
Shaded area contains preliminary information.
Notes:
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads.
12. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ .
10
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