M65761FP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M65761FP

QM-CODER

MITSUBISHI ELECTRIC  

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

(5) Interrupt Enable Register (W/R) (address : 3)

d7

d3

d0

IENB_REG : MP

0

SE ME DE JE

d0 (JE) :Temporary stop/End of trailer interrupt of initialization/coding/decoding/through .

(0:interrupt mask, 1:interrupt enable)

d1 (DE) :Coded data(Image data)read out/write in ready interrupt.

(0:interrupt mask, 1:interrupt enable)

d2 (ME) :Marker code detection interrupt during decoding. (0:interrupt mask, 1:interrupt enable)

d3 (SE) :SC count over error interrupt during coding.(0:interrupt mask, 1:interrupt enable))

This bit sets to 1 beforehand, it occurs the interruption when the SC counter is overflow during coding. Processing of coding

continues, but the correct coded data is not output.

NOTE:Bits,d0-d3,are for interrupt enable of bits d0-d2 and d4 of the Status Register.

The interrupt request signal(INTR) is asserted when any one of the status bit set in the interrupt enable (D0(JE)generates

interrupts even during the temporary stop),the status goes to "0" due to H/W reset or the INTR signal is negated when the

interrupt mask causes factors for interrupt to be lost. Moreever, the status register will not be cleared by the generation of

interrupts or the R/W of the interrupt enable register.

d7 (MP) :This specified the marker code detection time halt. (0:Continue/restart, 1:temporary halt)

Decoding will stop temporarily when the marker code is detected if this MP bit is preset to "1"during decoding. (it occures

interruption when the marker code is detected, if the ME bit preset to "1".)

if decoding is not completed during the temporary halt,it is possible to reset the line number setup

register. Next, if this MP bit is set to "0",decoding is restarted(Decoding continues to the line number set.)

(6) Register used to set the number of pixels (W/R)

(address:4)

d7

d0

PEL_REG_L :

PEL_L

(address:5)

d0-7 (PEL_L) :Number of pixels/line is set (Lower byte)

d7

d5

d0

PEL_REG_H : 0

PEL_H

d0-5 (PEL_H):Number of pixels/line is set (Upper byte)

It is possible to set up 8192 pixels maximum when 3-line template is used. It is used to set up 10240 pixels maximum when 2-line

template is used. The number of pixels actually coded (or decoded)should be set when reducing(or expanding).When the image

bus uses 16bits(or 32bits)in parallel I/F,multiples of 16 (or 32) should be set. In case of serial I/F,multiples of 8 should be used.

(7) Line Number Setting Register (W/R)

(Address:6)

(Address:7)

d7

d0

LSET_REG_L :

LSET_L

LSET_REG_H :

LSET_H

d0-7 (LSET_L):This sets the number of lines to be processed. (Lower bytes)

(1 to 65535, 0 line not used)

d0-7 (LSET_H):This sets the number of lines to be processed. (Upper bytes)

When reducing(magnification)the actual number of lines to be coded (decoded) should be set.The number of lines (relative number of

lines)from the process start command to be issued from now the immediately following temporary stop/end of trailer should be set. This

register should be set to the value specified before the process star command is issued. Moreover,this register can be rewritten during

processing as long as the following conditions are met:

• If the maximum value, (65535), is set before the process start command is issued,it can be reset once during processing.

• If a value other than maximum value (65535) is set before the process start command is issued and if resetting becomes necessary

during processing,the maximum value (65535) has to be reset once and desired value should the reset.

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