M65761FP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

Номер в каталоге

Компоненты Описание

Список матч

M65761FP

QM-CODER

MITSUBISHI ELECTRIC  

MITSUBISHI ICs (LSI)

M65761FP

QM-CODER

(13) This register sets up various functions (W/R)

(address:D)

d7

d0

CONV_REG : TP LI OB HO HR VR HE VE

d0 (VE):Selects expansion in lengthwise direction during decoding. (0:Equal dimension, 1:∗2 expansion)

d1 (HE):Selects expansion sideways during decoding. (0:Equal dimension, 1:∗2 expansion)

∗d0 and d1 are possible only during decoding.

d2 (VR):Selects reduction in lengthwise direction during coding. (0:Equal dimension, 1:1/2 reduction)

d3 (HR):Selects sideways reduction during coding. (0:Equal dimension, 1:1/2 reduction)

∗d2 and d3 are possible only during coding.

d4 (HO):Selects thinning in sideways direction during coding. (0:simple thinning, 1:OR processing)

This reduction is valid only during coding.

Note 1:This lengthwise 1/2 reduction during coding is used for the simple thinning. (Odd lines are skipped)

Note 2: The number of lines for image data to be inputs when VR=1 for coding must be twice the value set by the register which

sets the number of lines.

Note 3:The number of lines for image data to be outputs when VE=1 for decoding must be twice the value set by the register which

sets the number of lines.

d5(OB):This selects if the leading 1 byte is discarded during decoding. (0:Normal processing (No discarding),

1:The leading 1 byte is discarded)

If a command to start processing the first the stripe decoding is issued during decoding while OB is set to "1", the leading 1 byte

of the input data is discarded. (Not used for decoding) If OB=0,the one of byte discarding process is not used. (Normal decoding

used) For example, this function is used by the Host 16 bits bus when the leading 1 byte of the input data word is an invalid data.

Note :Selecting this function is valid in case of the Host 8 bits bus and the external context mode also.

d6 (LI):Line memory initialization is prohibited. (0:Initialization specified, 1:Initialization prohibited)

When a command to start processing coding/decoding of the first stripe is issued, if L1=1, the initialization of the internal line

memory is prohibited. (The last image data of the immediately prior coding/decoding left in the line memory is used as the

leading reference line data o the next coding/ decoding.) When LI=0, the internal line memory is initialized. (All white (0) data is

used as the leading reference line data of the next coding /decoding.)In case when the previous stripe ended with SDNORM

during coding/decoding of multi-stripe by setting this bit in the initialization prohibit (1).

Note :Even when LI=1is set, this LI bit is cleared (0) and the internal line memory will be initialized the same line due to the fact that

the H/W reset is written into the external reset terminal or the system set up register.

d7 (TP):This selects the Typical prediction when coding and decoding. (0:Typical prediction off, 1:Typical prediction ON)

11. 3 Initialization of register

Each register is initialized as shown in the table below by writing H/W reset to the external RESET terminals or the system set up registers.

Table 11. 5 Initialization values for registers

Registers

Initialization values

System set up

Parameter set up

Command

Status

Interrupt enable

Number of pixels set up

Set up number of lines

Number of lines processed

Data buffer

Marker code set up

Marker code read out

Various functions set up

00h Notes

00h

00h

00h

00h

00h

00h

00h

Inderfinite

00h

00h

00h

Note:When writing H/W RESET into the System

Setup Register,the value written into is set

up in the System Setup Register.

Share Link: