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RV5C386A-E2

I2C-Bus Real-Time Clock ICs with Voltage Monitoring Function

RICOH Co.,Ltd. 

PRELIMINARY

RV5C386A

12. GENERAL DESCRIPTION

(1) Interface with CPU

The RV5C386A is connected to the CPU by two signal lines SCL and SDA, through which it reads and writes

data from and to the CPU. Since the output of the I/O pin of SDA is open drain, data interfacing with a CPU

different supply voltage is possible by applying pull-up resistors on the circuit board. The maximum clock

frequency of 400kHz (at VDD≥2.5V) of SCL enables data transfer in I2C-Bus fast mode.

(2) Clock and Calendar Function

The RV5C386A reads and writes time data from and to the CPU in units ranging from seconds to the last two

digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two

digits are a multiple of 4. Also available is the 1900 / 2000 identification bit for Year 2000 compliance.

Consequently, leap years up to the year 2099 can automatically be identified as such.

*) The year 2000 is a leap year while the year 2100 is not a leap year.

(3) Alarm Function

The RV5C386A incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at

preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W

registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings

including combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and

"Saturday and Sunday". The Alarm_D registers allow hour and minute alarm settings. The Alarm_W

outputs from /INTRB pin, and the Alarm_D outputs from /INTRA pin. The current /INTRA or /INTRB

conditions specified by the flag bits for each alarm function can be checked from the CPU by using a polling

function.

(4) High-precision Oscillation Adjustment Function

The RV5C386A has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an

external crystal oscillator to configure an oscillation circuit. To correct deviations in the oscillation frequency

of the crystal oscillator, the oscillation adjustment circuit is configured to allow correction of a time count gain

or loss (up to ±1.5 ppm at 25°C) from the CPU within a maximum range of approximately + 189 ppm in

increments of approximately 3 ppm. Such oscillation frequency adjustment in each system has the following

advantages:

* Allows timekeeping with much higher precision than conventional RTCs while using a crystal oscillator with

a wide range of precision variations.

* Corrects seasonal frequency deviations through seasonal oscillation adjustment.

* Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC,

through oscillation adjustment in tune with temperature fluctuations.

(5) Oscillation Halt Sensing Function and Supply Voltage Monitoring Function

The RV5C386A incorporates an oscillation halt sensing circuit equipped with internal registers configured to

record any past oscillation halt, thereby identifying whether they are powered on from 0 volts or battery

backed-up. As such, the oscillation halt sensing circuit is useful for judging the validity of time data.

The RV5C386A also incorporates a supply voltage monitoring circuit equipped with internal registers

configured to record any drop in supply voltage below a certain threshold value. Supply voltage monitoring

threshold settings can be selected between 2.1 and 1.6 volts through internal register settings. The

oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to

the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the

supply voltage monitoring circuit can be applied to battery supply voltage monitoring.

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