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ZR36016 Просмотр технического описания (PDF) - Zoran Corporation

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ZR36016 Datasheet PDF : 36 Pages
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Integrated Color Space / Raster-To-Block Converter
Table 15: Decimation And Interpolation
HORZ
ZR36050 Image
Format
Bit
Decimation/
Interpolation [1]
Y
CB/CR
VERT
Compression Format and
Resolution
4:2:2
1
x
x
1
2:1:1 (Quarter Screen)
4:2:2
1
x
x
0
2:1:1 (Horizontal Half-Screen)
4:2:2
0
1
4:2:2 (Vertical Half-Screen)
4:2:2
0
0
4:2:2 (Full-Screen)
4:1:1 (H4V1)
1
x
1
2:1:1 (Quarter Screen)
4:1:1 (H4V1)
1
x
0
2:1:1 (Horizontal Half-Screen)
4:1:1 (H4V1)
0
1
4:1:1 (Vertical Half-Screen)
4:1:1 (H4V1)
0
0
4:1:1 (Full-Screen)
4:1:1 (H2V2)
4:1:1 (Full-Screen)
4:4:4
1
Each Component
1
2:2:2 (Quarter Screen)
4:4:4
1
Each Component
0
2:2:2 (Horizontal Half-Screen)
4:4:4
0
1
4:4:4 (Vertical Half-Screen)
4:4:4
0
0
4:4:4 (Full-Screen)
4:4:4:4
1
Each Component
1
2:2:2:2 (Quarter Screen)
4:4:4:4
1
Each Component
0
2:2:2:2 (Horizontal Half-Screen)
4:4:4:4
0
1
4:4:4:4 (Vertical Half-Screen)
4:4:4:4
0
0
4:4:4:4 (Full-Screen)
4:0:0 (1:0:0)
1
x
1
2:0:0 (Quarter Screen)
4:0:0 (1:0:0)
1
x
0
2:0:0 (Horizontal Half-Screen)
4:0:0 (1:0:0)
0
1
4:0:0 (Vertical Half-Screen)
4:0:0 (1:0:0)
0
0
4:0:0 (Full-Screen)
1. x = Decimation/Interpolation is performed on these components; – = Not performed or not applicable.
Minimum
Value
PXCLK to SYSCLK
Frequency Ratio
PAX
32
32
16
16
32
32
32
32
16
16
16
8
8
16
16
8
8
16
16
8
8
PAY
16
8
16
8
16
8
16
8
16
16
8
16
8
16
8
16
8
16
8
16
8
CKRT
0
1
1/2
1
1/2
1
1/2
1/2
1/2
1
1/2
1
1/2
1/2
1/2
1/4
1/2
1/4
1/2
1/4
1/4
1/2
1
1/2
1
1/2
1/2
1
1
1
1
Table 16 shows with shaded boxes which samples are dropped
or reconstructed respectively by the horizontal decimation or
interpolation process, for the various formats when HORZ = 1.
When filtering is selected with the HRFL bit, the value at time n
is [Y(n-1) + 2Y(n) + Y(n+1)]/4 on compression and is [Y(n-1) +
Y(n+1]/2 on expansion. When n is at the edge of a window, Y(n)
is copied and used for Y(n-1) or Y(n+1) as appropriate.
Table 16: The Horizontal Decimation/Interpolation
4:0:0
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
4:4:4
R
R
R
R
R
R
R
R
G
G
G
G
G
G
G
G
B
B
B
B
B
B
B
B
4:4:4:4 Y
C
Y
C
Y
C
Y
C
M
K
M
K
M
K
M
K
4:2:2
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6
4:1:1
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
(H4V1)
Cb0/Cr0
Cb4/Cr4
Figure 12 illustrates a typical case of data flow, from the PXIN
bus at the top through to the strip buffer, for an RGB input with
color space conversion to YCbCr and horizontal decimation,
with CKRT=1.
In this example, the internal pipeline delays of the various pro-
cessing stages are ignored. The example is also intended to
clarify the SYSCLK to PXCLK relationship. The strip buffer is
always operated at a rate of half the SYSCLK frequency. When
horizontal decimation is performed and CKRT=1, as in the
above example, the PXCLK rate (and the PXIN pixel rate) is the
same as that of SYSCLK. If horizontal decimation had not been
selected, or if CKRT=0, the PXCLK rate would have been half
the SYSCLK rate, the same as the strip buffer access rate.
15

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