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IDT72132

CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9

Integrated Device Technology 

IDT72132, IDT72142

CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9

COMMERCIAL TEMPERATURE RANGES

R

FF

SICP

SI

DATA OUT

t RFF

t RFFSI

t SICFF

0

1

n–1

(1)

t SIS

tA

NOTE:

1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.

Figure 8. Full Boundry Condition Timing

2752 drw 11

0

1

SICP

HF

HALF-FULL

t SICF

R

t SICF

AEF

7/8 FULL

AEF

ALMOST-EMPTY

(1/8 FULL-1)

n–2

n–1

HALF_FULL + 1

t RF

t RF

ALMOST FULL (7/8 + 1)

1/8 FULL

HALF-FULL

7/8 FULL

ALMOST-EMPTY

(1/8 FULL-1)

Figure 9. Half Full, Almost Full and Almost Empty Timings

2752 drw 12

RT

SICP

tRTC

t RT

tRTS

R

tRTS

EF, AEF, HF, FF

NOTE:

1. EF, AEF, HF and FF may change status during Retransmit, but flags will be valid at tRTC.

Figure 10. Retransmit

tRTR

0

1

FLAG VALID

2752 drw 13

5.36

8

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