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IDT72132

CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9

Integrated Device Technology 

IDT72132, IDT72142

CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9

LAST WRITE

NO WRITE

FIRST READ

R

SICP

FF

0

1

n–1

(1)

t SICFF

t RFF

COMMERCIAL TEMPERATURE RANGES

ADDITIONAL

READS

FIRST WRITE

0

1

n–1

NOTE:

1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.

Figure 5. Full Flag from Last Write to First Read

2752 drw 08

SICP

R

EF

DATA OUT

LAST READ

IGNORED

READ

FIRST WRITE

0

1

n–1

ADDITIONAL

WRITES

0

1

n–1

FIRST READ

t REF

tA

VALID

t SICEF

Figure 6. Empty Flag from Last Read to First Write

VALID

2752 drw 09

SICP

EF

R

DATA OUT

FIRST SERIAL-IN WORD

0

1

n–1

t SICEF

SECOND SERIAL-IN WORD

0

1

n–1

t RPE

tA

Figure 7. Empty Boundry Condition Timing

0

2752 drw 10

5.36

7

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