IDT72132 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72132 Datasheet PDF : 13 Pages
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IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Single Device Configuration
In the standalone case, the SIX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SICP clock, both of the
Data Set lines (D7, D8) go LOW and a new serial word is
started. The Data Set lines then go HIGH on the equivalent
SICP clock pulse. This continues until the D line connected to
NW goes HIGH completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of SICP.
SERIAL INPUT CLOCK
VCC
SERIAL DATA IN
SICP
SIX
NW
SI
Q 0-8
XI
D7 D8
PARALLEL DATA OUTPUT
GND
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
SICP
D7
D8
NW
2752 drw 16
Figure 13. Nine-Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1: RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Mode
Inputs
RS
FL/RT
XI
Internal Status
Read Pointer
Write Pointer
Reset
0
X
0
Location Zero
Location Zero
Retransmit
1
0
0
Location Zero
Unchanged
Read/Write
1
1
0
Increment(1)
Increment(1)
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
AEF, EF
0
X
X
Outputs
FF
1
X
X
HF
1
X
X
2752 tbl 09
5.36
10
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