CDP1851 Просмотр технического описания (PDF) - Intersil
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CDP1851 Datasheet PDF : 14 Pages
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CDP1851, CDP1851C
INTERRUPT CONTROL
Interrupt Enable/Disable
NOTES:
1. INT Enable = 1, INT Enabled
= 0, INT Disabled
2. A/B = 0, Port A
= 1, Port B
TABLE 4. (RA1 = 0, RA0 = 1)
7
6
5
4
3
2
1
0
INT
X
X
X
A/B
0
0
1
Enable
TABLE 5. (RA1 = 0, RA0 = 1)
7
6
5
4
3
2
1
0
Status Register
D7
D6
D5
D4
D3
D2
D1
D0
NOTES:
1. All Modes
(D0) B INT status (1 means set)
(D1) A INT status (1 means set)
2. Bidirectional Mode Only
(D2) 1 = A INT was caused by A STROBE
(D3) 1 = A INT was caused by B STROBE
3. Bit-Programmable Mode
(D4) A RDY input data
(D5) A STROBE input data
(D6) B RDY input data
(D7) B STROBE input data
TABLE 6. CPU CONTROLS
(NOTE 1)
CS
RA1
RA0
RD/WE
0
X
X
X
X
0
0
X
X
X
X
0
X
X
X
1
X
X
X
1
1
0
1
1
1
0
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
0
NOTE:
1. Read = RD/WE = 1 and WR/RE = 0 is latched on trailing edge of CLOCK.
WR/RE
X
X
0
1
1
0
1
0
1
0
1
ACTION
No-op bus three-stated
No-op bus three-stated
No-op bus three-stated
No-op bus three-stated
No-op bus three-stated
Read status register (Note 1)
Load control register
Read port A (Note 1)
Load port A
Read port B (Note 1)
Load port B
TABLE 7. MEMORY I/O USE
RD/WE INPUT
WR/RE INPUT
TPB INPUT
} PIO Terminal
I/O Space
Memory Space
MRD
MWR
TPB
MRD
TPB
} CPU Terminals
TPB
4-11
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