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CDP1851

CMOS Programmable I/O Interface

Intersil 

CDP1851, CDP1851C

TABLE 1. (RA1 = 0, RA0 = 1)

(NOTE 1)

MODE SET

7

6

5

4

3

2

1

0

Input

0

0

X

Set B

Set A

X

1

1

Output

0

1

X

Set B

Set A

X

1

1

Bit-Programmable

1

1

X

Set B

Set A

X

1

1

Bidirectional

1

0

X

X

Set A

X

1

1

NOTE:

1. Modes should be set in order as shown in Table 1.

If either port is set for bit-programmable mode, the two following control bytes should immediately follow:

TABLE 2. (RA1 = 0, RA0 = 1)

7

6

5

4

3

2

1

0

Bit-Programming (Note 1)

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

STROBE/RDY I/O Control (Notes 2 - 8)

D7

D6

D5

D4

D3

D2

D1

D0

NOTES:

1. Output = 1, Input = 0

2. (D1) 0 = Port A, 1 = Port B

3. (D2) 0 = No change to RDY line function, 1 = Change per bit (D6)

4. (D3) 0 = No change to STROBE line function, 1 = Change per bit (D7)

5. (D4) RDY line output data

6. (D5) STROBE line output data

7. (D6) RDY line used as:

Output = 1

Input = 0

8. (D7) STROBE line used as:

Output = 1

Input = 0

If interrupts will be used for either bit-programmed port, the following control bytes should be loaded.

TABLE 3. (RA1 = 0, RA0 = 1)

INTERRUPT CONTROL

7

6

5

4

3

2

1

0

Logical Conditions and Mask

0

D6

D5

D4

D3

1

0

1

NOTES:

1. (D3) 0 = Port A, 1 = Port B

2. (D4) 0 = No change in mask, 1 = Mask follows (See Table 3A)

3. (D5)(D6) 0, 0 = NAND; 1, 0 = OR; 0, 1 = NOR; 1, 1 = AND

TABLE 3A. (RA1 = 0, RA0 = 1)

INTERRUPT CONTROL

7

6

5

4

3

2

1

0

Mask Register (If D4 = 1)

B7 Mask B6 Mask B5 Mask B4 Mask B3 Mask B2 Mask B1 Mask B0 Mask

NOTE:

1. If Bn Mask = 1 then mask Bit (for n = 0 to 7)

4-10

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