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CDP1851

CMOS Programmable I/O Interface

Intersil 

CDP1851, CDP1851C

Programming

Initialization and Controls

The CDP1851 PlO must be cleared by a low on the CLEAR

input during power-on to set it for programming. Once

programmed, modes can be changed without clearing

except when exiting the bit-programmable mode. A low on

the CLEAR input sets both ports to the input modes,

disables interrupts, unmasks all bit-programmed interrupt

bits, and resets the status register, A RDY, and B RDY.

Mode Setting

The control register must be sequentially loaded with the

appropriate mode set control bytes in order as shown in Table

1 (i.e. input mode then output mode, etc.). Port A is set with

the SET A bit = 1 and port B is set with the SET B bit = 1. If a

port is set to the bit-programmable mode, the bit-programming

control byte from Table 2 must be loaded. A bit is programmed

for output with the I/O bit = 1 and for input with the I/O bit = 0.

The STROBE and RDY lines may be programmed for input or

output with the STROBE/RDY control byte of Table 2. Input

data on the STROBE and RDY lines is detected by reading

the status register. When using the STROBE or RDY lines for

output, the control byte must be loaded every time output data

is to be changed. To program logical conditions that will gen-

erate an interrupt, the interrupt control byte of Table 3 must be

loaded. An interrupt mask of the eight I/O lines may be loaded

next, if bit D4 (mask follows) of the interrupt control byte = 1.

The I/O lines are masked if the corresponding bit of the inter-

rupt mask register is 1, otherwise it is monitored. Any combi-

nation of masked bits are permissible, except all bits masked

(mask = FF).

INT Enable Disable

To enable or disable the INT line in all modes, the interrupt

ENABLE/DISABLE byte must be loaded (see Table 4). Inter-

rupts can also be detected by reading the status register

(see Table 5). All interrupts should be disabled when

programming or false interrupts may occur. The INT outputs

are open drain NMOS devices that allow wired O Ring (use

10K pull-up registers).

GENERATE CLEAR PULSE

AT PIN 13

SET PORTS A AND B

TO INPUT, OUTPUT, OR

BIT-PROGRAMMABLE MODE

USING TABLE 1

REPEAT FOR EACH

BIT-PROGRAMMABLE

PORT

REPEAT FOR EACH

BIT-PROGRAMMABLE

PORT

IS

YES

EITHER PORT

SET TO THE

NO

BIT-PROGRAMMABLE

MODE 3

PERFORM FOLLOWING

SEQUENCE BEFORE

PROGRAMMING PORT A TO

BIDIRECTIONAL MODE

SET BIT DIRECTION

USING TABLE 2

WILL

INTERRUPTS

BE USED FOR

NO

BIT-PROGRAMMED

PORT?

NOW SET PORT A TO

BIDIRECTIONAL MODE,

IF DESIRED

SET MASTER INTERRUPT

ENABLE/DISABLE

USING TABLE 4

MAIN PROGRAM

YES

SET BIT LOGICAL

CONDITIONS AND

MASKING USING

TABLE 3

NOTES:

FIGURE 3. A FLOW CHART GUIDE TO CDP1851 MODE PROGRAMMING

1. STROBE/READY I/O Control Byte (Table 2) is also used to output data to STROBE and READY lines when bit-programmed.

2. Status register (Table 2) is used to input data from STROBE and READY lines when bit-programmed.

3. Interrupt status is also read from status register.

4-9

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