CDP1851 Просмотр технического описания (PDF) - Intersil
Номер в каталоге
Компоненты Описание
Список матч
CDP1851 Datasheet PDF : 14 Pages
| |||
CDP1851, CDP1851C
Absolute Maximum Ratings
Thermal Information
DC Supply-Voltage Range, (VDD)
(Voltage Referenced to VSS Terminal)
CDP1851 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to+11V
CDP1851C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Device Dissipation Per Output Transistor
For TA = Full Package-Temperature Range
(All Package Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mW
Operating-Temperature Range (TA)
Package Type D, H . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
36
12
Maximum Storage Temperature Range (TSTG) . . . . -65oC to +150oC
Maximum Lead Temperature (During Soldering)
At Distance 1/16 ± 1/32 inch (1.59 ± 0.79mm)
from Case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions At TA = Full Package-Temperature Range. For Maximum Reliability, Operating Conditions Should be
Selected so that Operation is Always within the Following Ranges:
LIMITS
CDP1851
CDP1851C
PARAMETER
MIN
MAX
MIN
MAX
UNITS
DC Operating Voltage Range
4
10.5
4
6.5
V
Input Voltage Range
VSS
VDD
VSS
VDD
V
Functional Diagram
DATA
BUS
DATA
BUS
BUFFER
CLOCK
CS
RA0
RA1
WR/RD
RD/WR
TPB
CLEAR
ADDRESS
DECODE
AND
READ/
WRITE
LOGIC
SECTION
A
A0
A1
A2
A3
A4
A5
A6
A7
READY
STROBE
MODE
CONTROL
AND
STATUS
REGISTERS
A INT
B INT
INTERRUPT
MASKING
AND
LOGIC
SECTION
B
B0
B1
B2
B3
B4
B5
B6
B7
READY
STROBE
FIGURE 1. FUNCTIONAL DIAGRAM FOR CDP1851 AND CDP1851C
4-6
Share Link: 