PDI1394P25BY Просмотр технического описания (PDF) - Philips Electronics

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PDI1394P25BY

1-port 400 Mbps physical layer interface

Philips Electronics 

Philips Semiconductors

1-port 400 Mbps physical layer interface

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PDI1394P25BY

an acknowledge, but instead cancels the transmit operation and

releases the interface immediately; the LLC must not use this grant

to send another type of packet. After the interface is released, the

LLC may proceed with another request.

The LLC may request only one bus request at a time. Once the LLC

issues any request for bus access (ImmReq, IsoReq, FairReq, or

PriReq), it cannot issue another request until the PHY indicates that

the bus request was “lost” (bus arbitration lost and another packet

received), or “won” (bus arbitration won and the LLC granted

control). The PHY ignores new bus requests while a previous bus

request is pending. All bus requests are cleared upon a bus reset.

For write register requests, the PHY loads the specified data into the

addressed register as soon as the request transfer is complete. For

read register requests, the PHY returns the contents of the

addressed register to the LLC at the next opportunity through a

status transfer. If a received packet interrupts the status transfer,

then the PHY continues to attempt the transfer of the requested

register until it is successful. A write or read register request may be

made at any time, including while a bus request is pending. Once a

read register request is made, the PHY ignores further read register

requests until the register contents are successfully transferred to

the LLC. A bus reset does not clear a pending read register request.

The PDI1394P25 includes several arbitration acceleration

enhancements which allow the PHY to improve bus performance

and throughput by reducing the number and length of inter-packet

gaps. These enhancements include autonomous (fly-by)

isochronous packet concatenation, autonomous fair and priority

packet concatenation onto acknowledge packets, and accelerated

fair and priority request arbitration following acknowledge packets.

Then enhancements are enabled when the EAA bit in PHY

register 5 is set.

The arbitration acceleration enhancements may interfere with the

ability of the cycle master node to transmit the cycle start packet

under certain circumstances. The acceleration control request is

therefore provided to allow the LLC to temporarily enable or disable

the arbitration acceleration enhancements of the PDI1394P25

during the asynchronous period. The LLC typically disables the

enhancements when its internal cycle counter rolls over indicating

that a cycle start packet is imminent, and then re-enables the

enhancements when it receives a cycle start packet. The

acceleration control request may be made at any time, however, and

is immediately serviced by the PHY. Additionally, a bus reset or

isochronous bus request will cause the enhancements to be

re-enabled, if the EAA bit is set.

2002 Oct 11

27

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