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PDI1394P25BY

1-port 400 Mbps physical layer interface

Philips Electronics 

Philips Semiconductors

1-port 400 Mbps physical layer interface

Product data

PDI1394P25BY

12.0 OTHER DEVICE I/O

SYMBOL

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

See Note 1

—

56

—

mA

IDD

Supply current

See Note 2

See Note 3

—

40

—

38

—

mA

—

mA

IDD–PD Supply current in power down mode PD = VDD in power down mode

—

150

—

µA

390 kΩ resistor between cable power

VTH

Cable power status threshold voltage and CPS pin: Measured at cable power

4.7

—

side of resistor

7.5

V

VDD >= 2.7 V, IOH = –4 mA, ISO = VDD

2.4

—

VOH

High-level output voltage, pins CTL0,

CTL1, D0–D7, SYSCLK

VDD >= 3.0 V, IOH = –4 mA, ISO = VDD

2.8

—

Annex J: IOH = –9 mA, ISO = 0

VDD–0.4

—

VOL

Low-level output voltage, pins CTL0,

CTL1, D0–D7, SYSCLK

IOL = 4 mA, ISO = VDD

Annex J: IOL = 9 mA, ISO = 0

—

—

—

—

VOH

High-level output voltage, pin C/LKON VDD = 2.7 V, IOH = –4 mA; See Note 4

VDD >= 3.0 V, IOH = –4 mA; See Note 4

2.4

2.7

—

—

VOL

Low-level output voltage, pin C/LKON VDD = 2.7 V, IOL = 4 mA; See Note 4

—

—

IBH+

Positive peak bus holder current, pins

CTL0, CTL1, D0–D7, LREQ

ISO = VDD, VI = 0 V to VDD

0.05

—

—

V

—

V

—

V

0.4

V

0.4

V

—

V

—

V

0.3

V

1.0

mA

IBH–

Negative peak bus holder current, pins

CTL0, CTL1, D0–D7, LREQ

ISO = VDD, VI = 0 V to VDD

–1.0

—

–0.05

mA

II

Input current, pins LREQ, LPS, PD,

TEST0, BRIDGE, PC0–PC2

ISO = 0 V; VDD = 3.6 V

—

—

5

µA

IOZ

Off-state current, pins CTL0, CTL1,

D0–D7, C/LKON

VO = VDD or 0 V

–5

—

5

µA

IRST-UP

IRST-DN

VIT+

Pullup current, RESET input

Pulldown current, RESET input

Positive going threshold voltage,

LREQ, CTL0, CTL1, D0–D7, C/LKON

inputs

VI = 1.5 V or 0 V

VI = VDD, PD = VDD

ISO = 0 V

–90

—

.4

1.6

VDD/2 + 0.3 —

–20

µA

2.8

mA

VDD/2 + 0.9 V

VIT–

Negative going threshold voltage, LREQ,

CTL0, CTL1, D0–D7, C/LKON inputs

ISO = 0 V

VDD/2 – 0.9 —

VDD/2 – 0.3 V

VLIT+

Positive going threshold voltage, LPS

inputs

VLREF = 0.42 × VDD

—

—

VLREF+1

V

VLIT–

Negative going threshold voltage, LPS

inputs

VLREF = 0.42 × VDD

VLREF+0.2

—

—

V

VO

TPBIAS output voltage

At rated IO current

1.665

—

2.015

V

NOTES:

1. Transmit Max Packet (1 port transmitting max size isochronous packet (4096 bytes), sent on every isochronous interval, S400, data value of

0xCCCCCCCCh), VDD = 3.3 V, Tamb = 25 °C

2. Receive typical packet (1 port receiving DV packets on every isochronous interval, S100), VDD = 3.3 V, Tamb = 25 °C

3. Idle (1 Port transmitting cycle starts) VDD = 3.3 V, Tamb = 25 °C

4. The C/LKON pin is able to drive an isolation circuit according to Figure 5A-20 of the IEEE-1394a-2000 standard.

2002 Oct 11

11

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