PDI1394P25BY Просмотр технического описания (PDF) - Philips Electronics
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PDI1394P25BY Datasheet PDF : 42 Pages
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Philips Semiconductors
1-port 400 Mbps physical layer interface
Product data
PDI1394P25BY
LR0
LR1
LR2
LR3
LR(n–2)
LR(n–1)
Figure 14. LREQ Request Stream
SV01758
18.1 LLC service request
To request access to the bus, to read or write a PHY register, or to
control arbitration acceleration, the LLC sends a serial bit stream on
the LREQ terminal as shown in Figure 14.
The length of the stream will vary depending on the type of request
as shown in Table 11.
Table 11. Request Stream Bit Length
REQUEST TYPE
NUMBER OF BITS
Bus request
7 or 8
Read register request
9
Write register request
17
Acceleration control request
6
Regardless of the type of request, a start bit of 1 is required at the
beginning of the stream, and a stop bit of 0 is required at the end of
the stream. The second through fourth bits of the request stream
indicate the type of the request. In the descriptions below, bit 0 is the
most significant, and is transmitted first in the request bit stream.
The LREQ terminal is normally low.
Encoding for the request type is shown in Table 12.
Table 12. Request Type Encoding
LR1–LR3
NAME
DESCRIPTION
000
ImmReq
Immediate bus request. Upon
detection of idle, the PHY takes
control of the bus immediately
without arbitration
001
IsoReq
Isochronous bus request. Upon
detection of idle, the PHY arbitrates
for the bus without waiting for a
subaction gap.
010
PriReq
Priority bus request. The PHY
arbitrates for the bus after a
subaction gap, ignores the fair
protocol.
011
FairReq
Fair bus request. The PHY
arbitrates for the bus after a
subaction gap, follows the fair
protocol
100
RdReg
The PHY returns the specified
register contents through a status
transfer.
101
WrReg
Write to the specified register.
110
AccelCtl
Enable or disable asynchronous
arbitration acceleration.
111
Reserved
Reserved.
2002 Oct 11
25
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