PDI1394P25BY Просмотр технического описания (PDF) - Philips Electronics
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PDI1394P25BY Datasheet PDF : 42 Pages
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Philips Semiconductors
1-port 400 Mbps physical layer interface
Product data
PDI1394P25BY
For a bus request the length of the LREQ bit stream is 7 or 8 bits, as
shown in Table 13.
Table 13. Bus Request
BIT(S
)
NAME
DESCRIPTION
0 Start Bit
Indicates the beginning of the transfer
(always 1).
1–3 Request Type Indicates the type of bus request. See
Table 12.
4–6 Request Speed Indicates the speed at which the PHY
will send the data for this request. See
Table 14 for the encoding of this field.
7 Stop Bit
Indicates the end of the transfer
(always 0). If bit 6 is 0, this bit may be
omitted.
The 3-bit request speed field used in bus requests is shown in
Table 14.
Table 14. Bus Request Speed Encoding
LR4–LR6
DATA RATE
000
S100
010
S200
100
S400
All others
Invalid
NOTE:
The PDI1394P25 will accept a bus request with an invalid speed
code and process the bus request normally. However, during packet
transmission for such a request, the PDI1394P25 will ignore any
data presented by the LLC and will transmit a null packet.
For a read register request, the length of the LREQ bit stream is
9 bits as shown in Table 15.
Table 15. Read Register Request
BIT(S
)
NAME
DESCRIPTION
0 Start Bit
Indicates the beginning of the transfer
(always 1).
1–3 Request Type A 100 indicating this is a read register
request.
4–7 Address
Identifies the address of the PHY register
to be read.
8 Stop Bit
Indicates the end of the transfer
(always 0).
For a write register request, the length of the LREQ bit stream is
17 bits as shown in Table 16.
Table 16. Write Register Request
BIT(S
)
NAME
DESCRIPTION
0 Start Bit
Indicates the beginning of the transfer
(always 1).
1–3 Request Type A 101 indicating that this is a write
register request.
4–7 Address
Identifies the address of the PHY
register to be written to.
8–15 Data
Gives the data that is to be written to the
specified register address.
16 Stop Bit
Indicates the end of the transfer
(always 0).
For an acceleration control request, the length of the LREQ data
stream is 6 bits as shown in Table 17.
Table 17. Acceleration Control Request
BIT(S
)
NAME
DESCRIPTION
0 Start Bit
Indicates the beginning of the transfer
(always 1).
1–3 Request Type A 110 indicating this is an acceleration
control request.
4 Control
Asynchronous period arbitration
acceleration is enabled if 1, and
disabled if 0.
5 Stop Bit
Indicates the end of the transfer
(always 0).
For fair or priority access, the LLC sends the bus request (FairReq or
PriReq) at least one clock after the PHY-LLC interface becomes idle. If
the CTL terminals are asserted to the receive state (10b) by the PHY,
then any pending fair or priority request is lost (cleared). Additionally,
the PHY ignores any fair or priority requests if the Receive state is
asserted while the LLC is sending the request. The LLC may then
reissue the request one clock after the next interface idle.
The cycle master node uses priority bus request (PriReq) to send a
cycle start packet. After receiving or transmitting a cycle start
packet, the LLC can issue an isochronous bus request (IsoReq).
The PHY will clear an isochronous request only when the bus has
been won.
To send an acknowledge packet, the link must issue an immediate
bus request (ImmReq) during the reception of the packet addressed
to it. This is required in order to minimize the idle gap between the
end of the received packet and the start of the transmitted
acknowledge packet. As soon as the receive packet ends, the PHY
immediately grants control of the bus to the LLC. The LLC sends an
acknowledgment to the sender unless the header CRC of the
received packet is corrupted. In this case, the LLC does not transmit
2002 Oct 11
26
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