MPC9658 Просмотр технического описания (PDF) - Motorola => Freescale
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MPC9658 Datasheet PDF : 12 Pages
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MPC9658
Freescale Semiconductor, Inc.
APPLICATIONS INFORMATION
Programming the MPC9658
The MPC9658 supports output clock frequencies from 50
to 250 MHz. Two different feedback divider configurations
can be used to achieve the desired frequency operation
range. The feedback divider (VCO_SEL) should be used to
situate the VCO in the frequency lock range between 200 and
500 MHz for stable and optimal operation. Two operating
frequency ranges are supported: 50 to 125 MHz and 100 to
250 MHz. Table 7 illustrates the configurations supported by
the MPC9658. PLL zero-delay is supported if BYPASS=1,
PLL_EN=1 and the input frequency is within the specified
PLL reference frequency range.
Table 7. MPC9658 Configurations (QFB connected to FB_IN)
BYPASS PLL_EN VCO_SEL
Operation
0
X
1
0
1
0
1
1
1
1
X
Test mode: PLL and divider bypass
0
Test mode: PLL bypass
1
Test mode: PLL bypass
0
PLL mode (high frequency range)
1
PLL mode (low frequency range)
Ratio
fQ0-9 = fREF
fQ0-9 = fREF ÷ 2
fQ0-9 = fREF ÷ 4
fQ0-9 = fREF
fQ0-9 = fREF
Frequency
Output range (fQ0-9)
0-250 MHz
0-125 MHz
0-62.5 MHz
100 to 250 MHz
50 to 125 MHz
VCO
n/a
n/a
n/a
fVCO = fREF ⋅ 2
fVCO = fREF ⋅ 4
Power Supply Filtering
The MPC9658 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCCA_PLL power supply impacts the device
characteristics, for instance I/O jitter. The MPC9658 provides
separate power supplies for the output buffers (VCC) and the
phase-locked loop (VCCA_PLL) of the device. The purpose of
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it is
more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
VCC_PLL pin for the MPC9658. Figure 3. illustrates a typical
power supply filter scheme. The MPC9658 frequency and
phase stability is most susceptible to noise with spectral
content in the 100kHz to 20MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor RF. From the data sheet
the ICC_PLL current (the current sourced through the
VCC_PLL pin) is typically 12 mA (20 mA maximum), assuming
that a minimum of 2.835V must be maintained on the
VCC_PLL pin.
RF = 5–15Ω
CF = 22 µF
RF
VCC
VCC_PLL
CF
10 nF
MPC9658
VCC
33...100 nF
Figure 3. VCC_PLL Power Supply Filter
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 3. “VCC_PLL Power Supply Filter”, the
filter cut-off frequency is around 3-5 kHz and the noise
attenuation at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9658 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
MOTOROLA
For More Informa6tion On This Product,
Go to: www.freescale.com
TIMING SOLUTIONS
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