MPC9658 Просмотр технического описания (PDF) - Motorola => Freescale

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MPC9658

3.3V 1:10 LVCMOS PLL Clock Generator

Motorola => Freescale 

MOTOROLA

Freescale Semiconductor, Inc.

Order Number: MPC9658/D

SEMICONDUCTOR TECHNICAL DATA

Rev 3, 02/2003

3.3V 1:10 LVCMOS PLL Clock

Generator

MPC9658

The MPC9658 is a 3.3V compatible, 1:10 PLL based clock generator

and zero-delay buffer targeted for high performance low-skew clock

distribution in mid-range to high-performance telecom, networking and

computing applications. With output frequencies up to 250 MHz and

output skews less than 120 ps the device meets the needs of the most

demanding clock applications. The MPC9658 is specified for the

temperature range of 0°C to +70°C.

LOW VOLTAGE

3.3V LVCMOS 1:10

Features

• 1:10 PLL based low-voltage clock generator

PLL CLOCK GENERATOR

• Supports zero-delay operation

• 3.3V power supply

• Generates clock signals up to 250 MHz

• Maximum output skew of 120 ps

• Differential LVPECL reference clock input

• External PLL feedback

• Drives up to 20 clock lines

• 32 lead LQFP packaging

• Pin and function compatible to the MPC958

Functional Description

The MPC9658 utilizes PLL technology to frequency lock its outputs

onto an input reference clock. Normal operation of the MPC9658 requires

the connection of the QFB output to the feedback input to close the PLL

feedback path (external feedback). With the PLL locked, the output

frequency is equal to the reference frequency of the device and

VCO_SEL selects the operating frequency range of 50 to 125 MHz or 100

to 250 MHz. The two available post-PLL dividers selected by VCO_SEL

(divide-by-2 or divide-by-4) and the reference clock frequency determine

the VCO frequency. Both must be selected to match the VCO frequency

range. The internal VCO of the MPC9658 is running at either 2x or 4x of

the reference clock frequency.

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

The MPC9658 has a differential LVPECL reference input along with an external feedback input. The MPC9658 is ideal for use

as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.

The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the

selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL

bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not

apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also

causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and

close the phase locked loop, enabling the PLL to recover to normal operation.

The MPC9658 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept

W LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

transmission lines. For series terminated transmission lines, each of the MPC9658 outputs can drive one or two traces giving the

devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package.

© Motorola, Inc. 2003

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